Okay, I've figured out how the clock for the 4 stage shifter is done and gone back through and reworked all of the equations now that I'm a little more used to keeping track of whether I'm changing a NOR to an OR or an AND (depending on whether I want the output or the inputs inverted). This isn't to say I couldn't get it wrong, just less chance.Q1-5 is the 5 stage shift registerQ6-9 is the 4 stage shift register

AUDC	Q1in0000	1xx00	(Q5 XOR Q9) + !Q1*!Q2*!Q3*!Q4*!Q5*!Q6*!Q7*!Q8*!Q9yyxx	(Q5 XOR Q3) + !Q1*!Q2*!Q3*!Q4*!Q5

where xx = [01,10,11] and yy = [00,01,10,11](Whaddya know, I got it right.)Okay, the big AND term OR'd to the XOR is just a reset in case the shift registers get stuck. AUDC=0000 is easy to understand and matches up with what we know about TIA audio - always high. AUDC=xx00 links the two shift registers, while AUDC=yyxx decouples the two registers. It should be noted that the 5 stage shifter feeds the 4 stage shifter, not the other way around.Next is the clock for the 4 stage shifter. For those that care, the 4 stage shifter is clocked on the falling edge of T02 at the same time the 5 stage shifter is latched. So the T01 clock can be ignored unless you are doing hyper-accurate emulation of AUDC change timing (since the 5 stage shifter inputs are latched on the falling edge of T01).

AUDC	Q6-9 clkyy0y	T02yy10	T02 * !Q1*!Q2*!Q3*Q4yy11	T02 * Q5

The first is easy to understand, the clocks for the two shifters are the same. AUDC=yy11 means that the output of the 5 stage shifter is used as the clock of the 4 stage shifter. AUDC=yy10 creates the divide by 31 clock.Finally, the 4 stage shifter. I just realized that the inputs to the set/reset registers are active low, i.e. inverted. Which now makes the Z1 input !Z1 which then corresponds to the "pure" outputs. Oh drat, that means Z2in = !Z1 etc. Ahh, they even labeled the "real" positive outputs. So I've fixed my equations to reflect that.

AUDC	Q6in0000	100xx	(Q8 XOR Q9) + !Q6*!Q7*!Q8*!Q901yy	!Q610yy	Q511yy	Q6*!Q7*Q8+!Q8

This reveals the last bits of info, including the divide by three logic.No, I haven't created the test program to validate my equations to the known ones yet. All things in good time.