Mord's Blog

I don't know whether the timing would work out for such a thing, but such tricks have historically been quite common. The Defender arcade machine has IIRC 64K of RAM, of which 32K is located at the same addresses as the ROM. Any video read or processor write will go to that RAM bank; any processor read will come from ROM.

 

Likewise, in the Commdore 64, if ROM is enabled at $E000, any video reads or processor writes from that area will use the RAM, while processor reads will use the ROM. Disabling the ROM changes only the processor read function.

 

If one were to construct a 7800 cart with lots of RAM, it would probably be very useful to have separate banking controls for the CPU and Maria. One could thus have the CPU work with memory in one bank while Maria was busy displaying another. If timing allowed, it might even be useful to have three banks and include a function so that a read by the MARIA in one bank would write a zero into the corresponding address in another, while the CPU was able to access to the third. This could greatly accellerate games like Flight Simulator since the processor would not have to waste any cycles clearing out memory; every page of display data would be cleared before the microprocessor started using it.

I figgered if I managed to think up something like that, it'd have to be fairly obvious. Although the other things you mention I hadn't even considered. I was thinking timing shouldn't be a problem for using the halt line but I guess it depends on exactly what happens to Sally when it's halted. (Something I saw being discussed in the programming forum.)

 

If Sally stops immediately, then timing should be fine for switching to Maria's bank, as Maria has to spend some cycles looking up the first DLL before it dives into the ROM (IIRC Maria's lists are required to be in system ram due to timing requirements, as well as all within a single (or was it 2?) banks. 512 bytes rings a bell but it's been a while since I read the maria.txt file I downloaded a few years back. If Sally continues until it's current instruction is finished, it might be a problem due to it potentially trying to read (or write if there's cartridge ram) to Maria's bank - as we'd assume the HALT line has already gone up/down.

 

On the other hand, what if Sally was interrupted mid-instruction (As I believe they mentioned was the case) then when the halt line goes back down when Maria is finished, if Sally was just about to finish an instruction, would it still be in Maria's bank? Ideally this would be the case, and we'd just have to hope the rom can switch faster than Sally's cpu.

On the other hand, what if Sally was interrupted mid-instruction (As I believe they mentioned was the case) then when the halt line goes back down when Maria is finished, if Sally was just about to finish an instruction, would it still be in Maria's bank? Ideally this would be the case, and we'd just have to hope the rom can switch faster than Sally's cpu.

 

Good points all. The ROM can switch perfectly fast if the /HALT signal output is synchronized properly so it indicates who's actually performing a fetch. If the MARIA was willing to wait for the 6507 to finish its current operation before halting, it wouldn't need a special /HALT signal--it could just use "ready" for the purpose (which would stop on the next read operation). So I would expect /HALT operates instantly, and that MARIA synchronizes it in such fashion as to be useful. If they weren't going to make the /HALT signal on the cart port useful, I'd think they'd have put something more useful there instead (like maybe 3.579545MHz).

 

Incidentally, in a 6502-based system, each memory cycle has three distinct steps.

 

At the start of phase 1, the device controlling the bus outputs the memory address for the new cycle and indicates whether it's going to be a read or write.

 

At the start of phase 2, the device that's supposed to supply data will start putting it on the data bus.

 

At the end of phase 2, the device that's supposed to receive data will latch it off the data bus.

 

I would expect the /HALT signal to change state immediately following the end of phase 2 of a memory cycle.