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Introduction to processor hardware

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supercat

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In a classic microprocessor system (things like Pentiums and such get more complicated) the processor communicates with memory and I/O devices using a group of wires called the address bus, another group called the data bus, and a few individual wires which may be called control signals. In the case of the 6502, the primary control signals are called phi2 and R/W.

 

To read an address, the 6502 drives the address bus with the address it wants to read (e.g. if it wants to read address 1 0010 0011 0100, it will pull address lines 0, 1, 3, 6, 7, 8, 10, and 11 low (i.e. to ground), and address bits 2, 4, 5, 9, and 12 high (i.e. to a positive voltage--ideally +5, but in practice often more like +3.5) It also drives the R/W line high then some time later drives phi2 high.

 

The address bus and control signals are fed through some logic to determine which device should respond to that address. There should ideally be exactly one device responding to the requested address; it should drive the data bus with the requested data.

 

Some time after the 6502 drives the phi2 line low, it will latch the contents of the data bus wires and operate upon the data received. It will then drive phi2 low and begin the next cycle.

 

To write an address, the 6502 drives the address bus as before but it drives the R/W line low instead of high. Later, when the 6502 drives phi2 high, it will also drive the data bus with the data that it wants to write. This data will remain on the bus until very shortly after the processor drives phi2 low. Any device that wants to use the written data should latch it off the data bus when the phi2 signal goes low.

 

On the 2600, game cartridges don't have any connection to the phi2 and R/W signals, but this normally isn't a problem. The processor won't normally output any address in the range $1000-$1FFF except when reading from a game cartridge, and neither it nor anything else in the 2600 will mind if the ROM in a game cartridge starts driving its data on the bus as soon as the processor gives it the address (which is some time before the processor drives phi2).

 

The TIA chip in the 2600 will assume that the 6502 is talking to it if A12 and A7 are low. The RIOT chip will assume the 6502 is talking to it if A12 is low and A7 are high. Both devices are connected to all 8 bits of the data bus, but there's a little wrinkle when reading the TIA.

 

For a device to put data onto the data bus requires some moderately-beefy transistors. In designing the TIA, Atari only included output transistors for two of the data bus pins, D6 and D7. Consequently, when a read cycle is performed on the TIA, it's the only device that does anything with the data bus, and it only drives two of the bits. So what happens with the others? Nothing, at least not deliberately.

 

If a signal isn't driven high and it isn't driven low, what will happen to it is anyone's guess. It's possible to design a system so undriven signals will be weakly pulled high, or weakly pulled low, or weakly held in whatever state the seem to be in, but the 2600 doesn't do that. One might think of the state of an undriven wire as being like a feather sitting on the ground. If nothing disturbs it, it will remain wherever it happens to be. On the other hand, there's no particular assurance that nothing's going to disturb it.

 

In practice, undriven bits on the 2600 usually seem to keep the last state they were driven with. Many things can affect this, though, and good design must not rely upon such behavior. Otherwise, if using EPROMs, one may end up with things like games that work in with some brands of EPROM but not others, or even games that work the dark but not when the lights are on (light falling on an EPROM may slightly nudge undriven signals). Even if a game that relies upon such behavior seems to work today, there's no guarantee that it will work tomorrow.

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