Horizontal Sync
The horizontal and vertical counters are used to drive the rest of the digital logic in the circuit, but these counters cannot directly drive the synchronization of the CRT, for this horizontal and vertical sync signals are needed. Here is the circuit that generates the horizontal sync:
The two H5 NAND gates form an RS flip-flip. When pin 4 goes low, pin 6 will go high and stay high, until pin 10 goes low. At the end of a scan line /H RESET will go low which will set HBLANKING high and /HBLANKING low, this signals the start of the horizontal blank period. When the horizontal counter reaches 32, 32H goes high, which drives /HSYNC low; this is the start of the horizontal sync pulse. When the count reaches 64, 32H goes low, which drives /HSYNC high, ending the horizontal sync pulse. Finally when the counter reaches 80, pin 6 of G5 goes low, setting /HBLANKING high which ends the horizontal blank period. So from counts 0 to 31 just HBLANKING is low, for 32 to 63, HBLANKING and HSYNC are low, and from 64 to 80, only HBLANKING is low.
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