The vertical sync circuit works similar to the horizontal sync circuit. Again we have an RS flip-flop composed of two logic gates (F5), but this one is triggered by a high instead of a low. At the end of the vertical count, V RESET will go high, which will set VBLANK high which indicates the start of the vertical blank period. When the vertical counter reaches 4, the output of G5 will go low which is the vertical sync signal. When the count reaches 8, 8V goes high, the output of H5 goes low which turns off G5 and ends the vertical sync pulse. Finally when the vertical counter reaches 16, the RS flip flop is reset and VBLANK goes low which ends the vertical blank period. So, from counts 0 to 3, just VBLANK is on, from 4 to 7, VBLANK and VSYNC are on, and from 8 to 15, just VBLANK is on.

Finally the HSYNC and VSYNC signals are combined by this circuit to form the composite sync signal.