Paddles

Entry posted by Guest June 28, 2005

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There are two parts to the paddle generation circuit. There are two identical circuits (one for each player) that control the vertical position and height of the paddle, and a second circuit which controls the horizontal position and size.

The vertical circuit is based on the very versatile 555 timer chip (A9). In this case the 555 is configured in mono-stable mode. In this mode the OUT pin will go high when the TRIG input goes low, and will stay high for a period of time determined by the components connected to the CV and THR pins.

The cycle starts when 256V goes low, this starts the timer, set OUT high, which holds the binary counter (A8) in reset. The time that the timer output stays high is controlled by the variable resistor labeled Control; this is the player’s paddle control knob. The 50K variable resistor connected to the THR pin prevents the paddle from being enabled too early and thus being off the top of the screen. When the timer runs out the OUT pin will go low, releasing the reset on A8. Since pin 9 of B2 is high, the /HSYNC signal will clock the counter once every horizontal line. Since OUT is now low, pin 13 of B2 will high which sets /VPAD2 low, turning on the paddle display. When the counter (A8) reached a count of 15, the output of A7 will go low, which blocks the clock from getting to the counter through B2 and also causes /VPAD2 to go high. The result of this is that the paddle will be 15 pixels high.

This is the horizontal portion of the paddle circuit. The H3 flip/flop is used to set the horizontal width of the paddles. At the start of each horizontal line 128H is low, and the /Q output of H3 will be high, so the output of G3 will be high which turns off both paddles. When the horizontal counter reaches 128, 128H goes high, which sets pin 8 of G3 low. This will stay low for 4 horizontal counts when 4H goes high, setting /Q low. The sequence will also happen at horizontal count 384.

The final stage is composed of the two three input NOR gates G2. For the paddles to be on all three inputs to the NOR gate must be low. We just saw that the output of G3 will be low during horizontal counts 128-131 and 384-387. The /VPAD1 and /VPAD2 signals come from the previous stage and are only low for the 15 lines where each paddle is supposed to be displayed. The 256H signal control which paddle will be displayed. At the horizontal count of 128, 256H will be low, thus allowing /VPAD1 to control the PAD1 output. When the horizontal count is 284, /256H will be low, thus allowing /VPAD2 to control the PAD2 output.