Launch Missiles
Just finished getting the main kernel loop revamped to support updating the missiles. To make it work I unrolled the datastreams for both left and right PF0. PF0 only uses the upper half of the byte, while the missile enable only uses one of the bits in the lower half, so I combined the data(left PF0 with Missile 0 and right PF0 with Missile 1). Due to timing issues, I load those datastreams into the X and Y registers as that gives me more flexible for timing the writes (the PF0 writes have different windows than the ENAMx writes).
There's only 4 cycles left in the kernel if STA WSYNC is removed, so I don't think it's going to be possible to squeeze in the ball. There's 13 TIA updates per scanline though, so not too shabby!
The reposition's are currently NOP'ed out as I haven't revamped those yet. Have a problem where the Harmony's crashing, but not Stella, so I'm going to have to roll back to the prior version and reimplement all the changes while making sure I test on real hardware after each small change.
To make the kernel easier to understand, I made aliases for the DataFetchers.
DS_COLUP0 = DF0DATA DS_GRP0 = DF1DATA DS_COLUP1 = DF2DATA DS_GRP1 = DF3DATA DS_PF0L_M0 = DF0FRACDATA DS_PF1L = DF1FRACDATA DS_PF2L = DF2FRACDATA DS_PF0R_M1 = DF3FRACDATA DS_PF1R = DF4FRACDATA DS_PF2R = DF5FRACDATA KernelLoop: ; 70 lda #<DS_COLUP0 ; 2 72 sta WSYNC KernelLoopNoWSYNC: nop;beq RepositionP0 ; 2 2 sta COLUP0 ; 3 5 - before 25 lda #<DS_COLUP1 ; 2 7 nop;beq RepositionP1 ; 2 9 sta COLUP1 ; 3 12 - before 25 stx ENAM0 ; 3 15 - before 25 lda #<DS_GRP0 ; 2 17 sta GRP0 ; 3 20 - before 25 sty ENAM1 ; 3 23 - before 25 lda #<DS_PF2L ; 2 25 sta PF2 ; 3 28 - before 38 lda #<DS_GRP1 ; 2 30 - any sta GRP1 ; 3 33 - any sty PF0 ; 3 36 - PF0R, 28-49 lda #<DS_PF1R ; 2 38 sta PF1 ; 3 41 - PF1R, 39-54 lda #<AMPLITUDE ; 2 43 - any sta AUDV0 ; 3 46 - any lda #<DS_PF2R ; 2 48 sta PF2 ; 3 51 - PF2R, 50-65 ldy DS_PF0R_M1 ; 4 55 lda #<DS_PF1L ; 2 57 ldx DS_PF0L_M0 ; 4 61 - 0 triggers end-of-kernel stx PF0 ; 3 64 - PF0L, after 55 sta PF1 ; 3 67 - PF1L, 66 - 28 bne KernelLoop ; 3 70 - 2 69 not taken jmp KernelDone ; 3 72

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