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tf_hh

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About tf_hh

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    Stargunner
  • Birthday 10/11/1970

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    Male
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    Germany
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    Microelectronics, Atari 8-Bit Hardware, Atari 16-Bit Hardware, ATMEL Microprocessors

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  1. Absolute right. Atari buffers the R/W phase with a delayed PHI2 using the Delay Line. My suggestion is, that Atari engineers did this to solve some timing issues with the external 1064 memory expansion. Only the 600XL has this kind of delayed R/W signal at the PBI, all other systems with PBI or ECI hasn´t. That´s also the reason why you can´t remove the Delay Line and some other 74s chips when you install a 64 KB SRAM replacement. The internal 64 KB RAM works, but no external PBI device which needs R/W (... I think, all!) will. Of course I´ve mentioned this several times, also by email to the makers, but most sellers offering such products keep on their infos "You can remove Delay Line and (all) 74s chips from the DRAM circuit". But who I am to spread the truth... 😁
  2. The german developer at the former Compy-Shop company decide to use the 130XE banking scheme as the base for their circuits. So all software using the special modes (ANTIC selects expanded memory OR CPU selects expanded memory OR both!) existing on every stock 130XE would run with their solution. The 130XE has only four banks, but you need sixteen banks to enable 256 KB expanded memory. So the guys at Compy-Shop uses PB6 and PB7 to have four banks easily switchable. This logic was simple to made without any PLD. Maybe (just my suggestion) because the XE series wasn´t much common in the U.S., the U.S. companies provided memory expansions didn´t implement the XE mode and their products always map the expanded memory for both processors - ANTIC and CPU. So the PB5 bit is used for bank selection. 256 KB "RAMBO" style uses PB2, PB3, PB5 and PB6 for bank selection - what makes the logic circuitry easier than the Compy-Shop way. 512 KB RAMBO needs the same effort (latching PB7).
  3. Yes. IMHO I would say, the chance to grab one with a defect PAL GTIA is 50 percent. But it´s not a big thing. Several people have now spare GTIA´s from a Sophia-2 install. You can also switch to Sophia-2, which replaces the GTIA fully. Or buy a GTIA Fixer from me or make the little circuit by hand yourself 🙂
  4. Sure, but I never seen one. I have had some 1064 with cardboard boxes in my hand, but there never was any paper with it. When I´m remembering right, on the back side were some "instructions" how to attach it to the 600XL in several languages. Maybe one owner of the 1064 complete-in-box may sent a picture here.
  5. User docs? Didn´t know about any. But... when there´s something, what may be printed on it more than "Plug the 1064 into your computer´s parallel connector and you´re done"?
  6. Using standard CAS and RAS signals attached to the PBI. RAS is always active (for internal and external DRAM), because it´s needed for DRAM refresh. CAS (the CAS signal at the PBI) is latched using the 74LS32 and the 74LS375. As long A14 and A15 are low, the CAS transistions are only mapped to the internal DRAM. External CAS signal remains high. The simple reason why Atari design it this way: There was no possibility to "turn off" the internal DRAM without disabling the whole DRAM circuitry (like modern expansions do this with setting EXTSEL to low). So Atari can´t make another way to integrate the external expansion w/o modding the 600XL.
  7. I would suggest not to focus on PBI device or - design. The 1064 uses RAS and CAS lines, IMHO these signals are only attached to the PBI to support the 1064. Later XE machines haven´t these signals at the ECI. And, the first XL O.S. version (rev. 1) found in early 600XL machines hasn´t any PBI support as we know it from today. So if you have an O.S. ROM with the marking CO62024 instead the well-known CO61598, no PBI device like the KMK-IDE or MSC or the BlackBox won´t run, because this O.S. hasn´t the PBI protocol built in. You could make run / use the 1064 completely. Remove the 74LS32 chip and make a bridge between pin 8 and 10. The disables the "CAS16K" generation, so CAS (at the PBI) is enabled for all adresses to the PBI, and not only for adresses from $4000 up. Of course you must remove existing DRAM chips from the 600XL mainboard 🙂
  8. Why ever, but Atari did design it this way. When the 1064 is plugged to the 600XL, only the "last" 48 KByte ($4000-$FFFF) are mapped external. The first 16 KByte are always used internal. Easy test: Remove the both internal DRAM Chips - your 600XL won´t start 🙂 The internal wires are only needed to expand the multiplex address space from 16K to 64K. The inputs for the highest addresslines A14 and A15 are fixed to ground at the 600XL mainboard, so only A0...A13 is used, which means 16K address space. So the wires just add the missing both address lines and the 3rd one will enable generation of "CAS" for the whole 64 KB address space - by default it´s internal limited to 16K, too.
  9. The switch enables/disables the color generation. So if you set the switch to "no color", a multi-norm TV will switch to "PAL". If color enabled, it will switch to "SECAM". SECAM Atari computers always have no RF modulator.
  10. When there´s some demand, it´s no problem the create an external version of the 576 KB expansion for a good price. But Steve has to make the case
  11. The PM V2 document showed two 10 uF caps in line of L-Audio Analog and R-Audio Analog. Are these caps now on the PM V3 PCB installed or it´s useful to add them? If so, they should be shown in this picture.
  12. That is correct. Yellow = White and Red = Brown 🙂 Sorry, I didn´t found the time to update the manuals. The old cable is EOL 😞
  13. All Speedy versions work fine with the 2797, no issues known.
  14. Just to be sure, the following order must be used: 1. Power-On the 1050 without mechanics attached (for easier access). Also remove the Speedy or similar 2. While powered on, set a jumper between TP8 and TP9 3. Check pin 16 If the jumper was placed before power is switched on, the FDC doesn´t enter the test mode correct. Check pin 37 of FDC and pin 13 of the RIOT (6532) about continuity, these both pins are directly connected. Test (in standard usage mode, with standard ROM or with Speedy) the pin 37 of the FDC. Start DOS, give a single-density format command. Pin 37 of the FDC must be high. If a medium/enhanced density or double density (only with Speedy) format is sent, the pin 37 must be go to low. If not and continuity to 6532 is given, replace RIOT, then FDC itself.
  15. Sorry, wasn´t online some days here. Interesting find with the "gap" in the power trace, but it seems to be standard for this board revision: This is the same 65XEN mainboard and it also have this gap. I checked it against the schematics and reason is the seperation of +5V from standard to the 4050 buffer and video amp stage. There´s a coil between to filter the 5 volts. I´m pretty sure the developer saw the wrong routing after the final production mask was made and scratch these gap by hand from the mask. However, IMHO the first problem is the power switch itself regarding your posts here. I´ve often have had bad power switches. So exchange them first or solder for test a permanent bridge and plug/unplug the power. Now the black screen behaviour should be constant. The board you have is a PAL mainboard with PAL chips on it. You didn´t set your location in your profile, so if you´re living in NTSC areas, a black screen is normal. More typical is a red/brownish screen (PAL) or greenish (NTSC) when the computer has memory failures. Black scren - when T.V. norm is capatible - is more something around bad CPU, bad ROM, bad DRAM logic.
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