ClausB

From Atmel: "The ATF1500 has 32 I/O pins and 4 input-only pins. Each I/O pin is associated with a logic macrocell containing a flip-flop." Here's what we need: 16 cells for data register and all 12 input pins 4 cells for bank register and 4 SRAM address pins 2 cells for mode register 1 cell and pin for SRAM -WE 4 cells and pins for Luma outputs That's 27 cells with 21 I/O pins so far. That leaves 5 cells with 5 I/O pins plus 10 I pins for miscellany, including the clock multiplier, which is still nebulous. So it appears the Atmel ATF1500 might work.

We need at least this many signal pins on the CPLD: Inputs: 8 for D0 - D7 1 for -D5xx 1 for Phi2 1 for R/-W 1 for -S4 or -S5 Outputs: 4 for SRAM A13 - A16 1 for SRAM -WE 4 for Lum0 - Lum3 Total: 21 I/O pins What have I missed?

I answered the previous post in the old thread.

1. That's right, the enhanced video signal is summed, or piggy-backed, onto the Atari video signal. By itself it contains no color information, just brightness levels, so the Atari mode will supply the color. 2. No, the two signals are simply added, so one cannot mask or subtract from the other. 3. Good question. I hadn't thought about that. Since this circuit relies on ANTIC DMA to generate video, it is really only useful with ANTIC's single-line graphics modes (E and F) and not with the character modes or the lo-res graphics modes. In modes E and F, vertical scrolling is done by modifiying the bitmap address in the display list, so that will also cause the enhanced video to scroll properly. With horizontal scrolling, ANTIC shifts its DMA by one cycle for every two color clocks of scrolling. So that should work too, but only with two color clock resolution. Yes, PMG are unaffected. And there is no priority between PMG and the enhanced luma. That is, PMG cannot mask the luma and vice-versa, as in answer #2 above.

It will plug into the cart slot and, with a short cable, into the audio/video connector. Its S-video connector will output the enhanced video. No need to open the Atari or solder anything. It will have 128K bytes of RAM, banked within the 8K cart space. It will assume that, while the enhanced display is active, any read from that 8K space is ANTIC DMA and it will read the SRAM and spit out luma. DLIs can enable it just before the top of the display and disable it just after the bottom, and the programmer will have to be careful not to read that 8K in the interim, lest he get sparkles. I'm tending to favor the idea of using the right cart space ($8000-$9FFF) instead of the left space, for at least two reasons: - The XL OS doesn't like it when you switch RAM/ROM contents above $BFF0. - It would allow built-in BASIC to run.

We'll concentrate here on the Stage 2 design, which should fit into a CPLD and a 128K x 8 bit SRAM. We need at least this many flip-flops in the CPLD: Luma data register: 16 bits (2 reads from SRAM) Mode register: 2 bits (3 display modes plus off) Bank select register: 4 bits (16 8K banks) Clock multiplier: 3 bits (1.8 MHz * 8 -> 14.3 Mhz) Total: 25 FFs Have I forgotten anything?

Some timing diagrams to chew on: Normal ANTIC DMA Read Cycle - 559 ns ___________________________ Phi2 \___________________________/ \ _ __________________________________________________ A0-15 _XXXXXX__________________________________________________ _ ___ D0-7 _>-----------------------------------<XXXXXXXXXXXXXXXX___ Double (LEM Stage 1) Read Cycle ___________________________ Phi2 \___________________________/ \ _ ______________________ ___________________________ A0-14 _XXXXXX______________________X___________________________ Bank 1 Bank 0 _ ______________________ __________________________ D0-7 _XXXXXXX______________________X__________________________ Triple (LEM Stage 2) Read Cycle ___________________________ Phi2 \___________________________/ \ _ ______________________ _____________ _____________ A0-14 _XXXXXX______________________X_____________X_____________ Bank 2 Bank 1 Bank 0 _ ______________________ _____________ ____________ D0-7 _XXXXXXX______________________X_____________X____________ The normal cycle has lots of dead time from when the address lines are stable to when the data lines need to be stable, because memory circuits were slow back then. ANTIC does not sample the data lines until the end of the cycle, when the Phi2 clock signal goes low. The LEM SRAM is much faster so we can squeeze more read cycles into each ANTIC cycle. The data from Banks 1 and 2 become the enhanced luma, while the Bank 0 data go to ANTIC as before.

Recap: This is what I envision for Stage I, which has two banks, one for ANTIC and one for enhanced luma. It will have an 8-bit shift register, a 7.2 MHz clock, and up to 3 modes: 80 horizontal pixels of 16 brightness levels; 160 pixels of 4 levels; 320 pixels of 2 levels. Of course, these all overlay the regular ANTIC/GTIA display. The first mode is like an extra GR.9 mode. When overlaid on a GR.11 screen, 256 simultaneous colors would be available, without DLIs. The last mode is like an extra GR.8 mode. Stage II would use three banks, a 14.3 MHz clock, and a 16-bit shift register. Possible modes are: 160 horizontal pixels of 16 brightness levels; 320 pixels of 4 levels; 640 pixels of 2 levels. The last mode could provide clear 80-column text with background colors provided by ANTIC/GTIA. Stage III could use all four banks and a 24-bit shift register, if the Atari data bus can be switched that fast. Among its modes could be 160 horizontal pixels of 64 RGB-like colors (2 bits per R, G, and B, encoded into NTSC).

We have started a new thread in the Hardware forum for developing the design we started here. The development is an open collaboration, so if you have specific, valid contributions to the design, please post them there. General questions and comments should still go to this thread, please.

This new thread is for developers of the video upgrade we started designing in this old thread. The development is an open collaboration, so if you have specific, valid contributions to the design, please post them here. General questions and comments should go to the old thread, please.

This is the truest C64 emulator I've found:

IMO 6502 opcodes should be in CAPS - lower case is for Intel code. Labels can be mixed case, like EndOfKernel, and never, NEVER use those horrid underscore things!

Brilliant work! And thanks for the ACK.

If you prefer tables over graphs:

Here's Atari's say on the topic, from this document: http://www.atariage.com/forums/topic/134096-antic-on-a-breadboard/page__p__1617584entry1617584

From the Rambo manual:

x

If you have a Buchholz/Rambo/Wizztronics 256K upgrade then you can already access that extra 2K. When you select bank #3 (by setting PORTB to $8D, for example) then the entire upper 16K of main RAM (that under the 14K OS and the 2K I/O) appears in the bank area ($4000-$7FFF). So the 2K normally under the I/O would appear at $5000-$57FF.

Ok, that's what I thought. They're of no use to me. Maybe I'll keep them and give them to someone to tinker with? Tempest I could use a new CPU for my prototype 800. See here: http://www.atariage.com/forums/topic/122471-atari-800-engineering-serial-26/page__view__findpost__p__1504131 Please PM.

The RASTIME signal on cart pin S has the same falling edge as Phi2 but the rising edge is advanced by about a quarter cycle. An LRC delay line (total time constant of 132 ns) and a NAND gate on the Personality Board generate the signal. So, any cart that uses the falling edge (to clock data, for example) would see no difference between the 800/400 and XLs. Any that uses the rising edge to latch the address (as the OSS banking carts do) would also work with both. I doubt it is necessary to change the signal in your mod. BTW, I presume you've noticed the RASTIME and /WRITIME errors in the Hardware Manual schematics. In the Personality Board schematic, those two signal names are swapped. Also, in the 800 Motherboard schematic, the pin labels for those two signals are swapped. You can see the errors if you compare with the equivalent circuit in the 400 Motherboard schematic. I also verified it by tracing the circuits in an 800.

Very cool. Any tech details or pics of the inside? Which motherboard? What LCD? Separate luma & chroma or composite? Anything?

1. That's right, the enhanced video signal is summed, or piggy-backed, onto the Atari video signal. By itself it contains no color information, just brightness levels, so the Atari mode will supply the color. 2. No, the two signals are simply added, so one cannot mask or subtract from the other. 3. Good question. I hadn't thought about that. Since this circuit relies on ANTIC DMA to generate video, it is really only useful with ANTIC's single-line graphics modes (E and F) and not with the character modes or the lo-res graphics modes. In modes E and F, vertical scrolling is done by modifiying the bitmap address in the display list, so that will also cause the enhanced video to scroll properly. With horizontal scrolling, ANTIC shifts its DMA by one cycle for every two color clocks of scrolling. So that should work too, but only with two color clock resolution.

Thanks to all who volunteer their scarce time. The version we've called Stage 2 will triple the Atari's video bandwidth. That is, it will offer monochrome graphics modes with double the original resolution, to be overlaid onto the Atari's original colorful modes. For example, one mode gives 160 pixels of 16 brightness levels crossed with the 16-color GTIA mode to produce up to 160 out of 256 colors per scanline. Other modes offer 320 pixels of 4 levels or 640 pixels of 2 levels, allowing clear 40- or 80-column text with colorful backgrounds. It will plug into the cart slot and, with a short cable, into the audio/video connector. Its S-video connector will output the enhanced video. No need to open the Atari or solder anything. It will have 128K bytes of RAM, banked within the 8K cart space. That's more than enough for Rybags' interlaced display, which could offer up to 640 by 400 resolution.

It is on the back burner, I'm afraid. Different year, same reasons: Summer is too busy and too short around here and Fall is for FIRST Lego League robotics. Looks like Winter before I can make much progress. I do take time now and then to think about the design. It might go faster if we get a collaboration going. If I could work with someone who has CPLD development tools and experience, and someone with PCB layout capability, we might just get something done. Anyone interested?

More broken links in this old post: http://www.atariage.com/forums/topic/33233-sorted-table-of-contents/page__view__findpost__p__385383