Jump to content

flashjazzcat

Members
  • Content Count

    16,177
  • Joined

  • Last visited

  • Days Won

    25

flashjazzcat last won the day on August 14 2019

flashjazzcat had the most liked content!

Community Reputation

10,699 Excellent

About flashjazzcat

  • Rank
    Quadrunner
  • Birthday 12/19/1972

Contact / Social Media

Profile Information

  • Gender
    Male
  • Location
    United Kingdom
  • Interests
    Playing jazz guitar, music, reading, writing, PCs and anything to do with computers, movies

Recent Profile Visitors

68,073 profile views
  1. Yes: I read the posts but I'm still at a loss as to where the custom SIO loader which is more or less taken as a given is actually to be found. I would have speculated that the VBI code which flashes the colours and (AFAIK) updates the progress bar is causing an issue during high speed SIO, but I have just tested the Yoomp! ATR from the Yoomp! website on real hardware, using RespeQt at divisor 0 and Hais' HSIO driver (in the U1MB PBI BIOS), and the game loaded at full pelt with no errors. Maybe the issue is confined to NTSC systems (this was PAL), but if there's a custom SIO loader, I can't find it. I've tried divisor 6 on the same machine and it stalls after a while. I've seen issues with stuff at slower speeds before, ironically enough, so it's not unprecedented.
  2. What happened? I have some strange issues of late which are apparently not easy to reproduce.
  3. Which version of Yoomp! uses a custom SIO loader? I've yet to encounter a version which is anything other than a standard multi-segment binary file which does no direct handling of IO whatsoever. If this were not the case, I would not expect it to run from the SIDE loader. Even the ATR version simply has a boot loader which automatically selects the PAL or NTSC XEX and runs it.
  4. The SIDE2 banking register is at $D5E4, so writing to $D503 will do nothing at all with these patched OSS ROMs. I treat ebiguy's patched ROM as a black box, so hopefully he will chip in.
  5. Consider it a learning experience. I made these videos entirely off my own back but users are still inventive enough to find something to nit-pick about.
  6. The pin numbers do not change because of the orientation of the IC.
  7. Indeed. Only the OS RTC at would be off, but you could always update that via your own interrupt handler if this were a concern.
  8. There are a couple of instances in which PBI handlers may call the OS; most notably if they are registering an entry in HATABS (in which case they will call NEWDEV). The problem is, the handler will probably assume the OS database is present in low RAM, and potentially wipe out any locations you've overloaded for other purposes (hard disk drivers will typically interact with the zero page DCB variables). The most practical means of using RAM under the OS is to simply re-enable the ROM every time you call the OS and then disable it again afterwards, but doing so won't increase the amount of zero page memory you can use. I was faced with the same dilemma when writing the graphical OS. If the OS has any hope of working well with PBI handlers (including U1MB/SIDE hard disks and PBI-accelerated SIO using Hias' driver), having the stock OS code and variables where they are supposed to be is probably a good idea.
  9. If you have U1MB, you can mount 32MB FAT-hosted ATRs and make raw sector copies of your partitions at around 35KB/s R/W speeds, then copy the ATRs back off the card for archiving.
  10. It's in the forward position, which is to say R/W.
  11. ATR mounting without U1MB PBI support is coming along (developed and debugged wholly on real hardware): Naturally the selection of ATRs which will actually work using this solution is relatively small, but I thought the facility was worth adding, as promised.
  12. I actually encountered the same issue when updating a stand-alone SIDE2 the other day. The SDX SIDE.SYS driver supplied on the non-FJC firmware device driver in use was NINE YEARS OLD, however (version 1.0), so I was hardly surprised: The SDX build is seven years old, meanwhile. I don't observe any issues once SDX and the driver are up to date, and my workaround was also simply to use the SIDE2.COM flasher which I also provide on the firmware ATR.
  13. The 1200XL motherboard is the superior to the XE motherboard in almost every sense, and has the distinct advantage of already neatly fitting into a 1200XL case. Upgrades like U1MB and SIDE2 have made the PBI bus somewhat redundant in the vast majority of situations, and converting the 1200XL to otherwise full XE compatibility without replacing the motherboard is relatively trivial. With Bob's mod, 1200XL video is better than that of a typical XE. The 1200XL I modded for 5V PSU, PBI, etc, some years ago now seems like overkill and I never plugged anything into the PBI connector during normal use. Fortunately I have another three in stock condition and will be upgrading one of them in a far less disruptive manner at some point in the future. About the only thing I can say is that I would be impressed to see such a motherboard transplant which doesn't end up looking like a computer which had some other computer's motherboard shoved into it, poorly finished case modifications performed on it, and various superfluous, gaping holes left where the original ports used to be.
  14. Those CPU board connections: check them about a dozen times. Not that I'm saying they're wrong, but there are two different chip layouts on the CPU boards and it's very easy to solder wires not only to the wrong legs of ANTIC, but even to entirely the wrong chip. The Incognito will work without these two connections (they are there to provide ANTIC extended RAM access), so if absolutely desperate, try the machine with those two jumper wires disconnected.
×
×
  • Create New...