TurkeyMan

i think you might be misunderstanding me too each 'NOR gate' as i was putting it is actually a single transistor. each of those little circle connections is clearly a single transistor, but the question is how it is connected which gives it implied logic. it can work one of 2 ways, the source line feeds the base of a transistor at the circle, and it either a) opens the transistor to continue down the line, allowing the signal to remain high (an effective AND as you describe), or b) open a connection to ground, which would drive the signal low (resulting in an effective NOR down the line as i suggest). it's precisely the same number of circuit components either way. and the logic difference is subtle, but i'm still fairly convinced it's the only way it could work in the context of the sudio circuit :/ unlike the address decoding circuit you're looking at, in the case of the circuit i'm studying, the lines ARE directly connected at the horizontal line at the top, Q and /Q both connect and it would always result in the top lines state being low under any circumstance assuming ANDing logic. can you explain how i could interpret that part of the circuit using your theory? anyway, at the end of the day, i did manage to get my emulation of that circuit working.. seems to sound correct, so i don't really need to stress over it anymore. but yeah, it is still a very strange schematic.. very unconventional :/ thanks for all the input guys!

Hard for me to comment without taking some time to study this section of the circuit. Although at a glance, it appears to work under the same conclusions I've made with the other circuit. It's hard to say what state each wire coming from the address latches represent. I can see the incoming lines are obviously inverted, but they appear to pipe through 2 latches, the final one outputs Q and /Q to the address matrix, and it is very unclear which is Q or /Q. As I see it, the matrix decodes: VSYNC = /(A0|A1|A2|A3|A4|...) - ie, the VSYNC line goes hi only when all incoming lines are low (NOR). I can't say without considerable study what /W and O2 actually are, but I'm sure they fit the puzzle. The reason I must come to this conclusion, is that if you apply your theory to my other circuit, the logic doesn't actually work at all. Various connections, particularly the wiring together of Q and /Q from the incoming D2/D3 latches cause the output of the circuit to be low under absolutely every circumstance.

Cool, this is precisely what I just suggested in my last post. It's the only way I could see that any of it could work, so it's encouraging to know someone else came to the same conclusion I just have to get some time to write out my truth tables for all these lines and test it.

Okay so i've considered all these ideas, and i've come to some new conclusions, which seem to work better (still haven't tested if it's correct, have to work through the circuit yet....) I initially assumed these were open-drain gates, but i realised that they can't be, since there are many parts of the circuit that would need pull up resistors if that were the case, and there aren't any. But what i'm actually thinking is that these components are driven TTL, and that those circle connection components are actually the inverse of what i expected. Consider if each circle marker were a transistor connecting the target line with ground. If the latches output HI, the transistor turns on and the pull up line goes low. This means the line becomes a long NOR, which may actually make this circuit begin to work! Time to start writing up some truth tables...

Sorry to double post, you replied while i was also replying This is what I expected, but unless there is a mix of the 2, and they are distinguished in some way I can't recognise, then the circuit doesn't appear to work assuming they all either ANDs or ORs... If they are all ANDs, then the top line will always be low, since both Q and /Q are wired together, and at least one will pull the whole circuit low. If they are all ORs, then the top line will always be high for the same reason. Perhaps my assumption about the D3-4 latches is actually wrong, and they are not SR latches like the 4bit shift on the right... But that was my best guess. It's a particularly tricky circuit to read. There seems to be a fair bit of information missing. :/

The Stella Programmers Guide doesn't make any mention to the audio waveform generation logic. It just mentions that there is a control register that changes the waveform, and expects you to experiment. :/ Well this is what i initially thought, but the circuit doesn't appear to work under that assumption. If you look at the top of the schematic, some lines intersect as a regular looking point, that seems like a regular intersection to me. But the ones I'm interested in have a circled +, and on many of these there is a little 'T' looking thing hanging out one side. I'm pretty convinced it's some sinister component. And to support that theory, notice in the run of 5 lines i refer to, each line is powered by a pull up resistor down the bottom, then they all meet at the single line up the top, which is also powered by its own pull up resistor. If these were just regular line intersections, then there's no reason to have 6 resistors, and the presence of those extra resistors would probably fry the latch. Also the circuit would be flawed since Q and /Q are both wired together in at least 2 cases... :/ It's here: http://www.atariage.com/2600/archives/sche...A_1A_2048_4.zip (From this website in Atari2600/Archive/TIA Schematics)

Hi people I'm working on a 2600 emulator, and I'm currently trying to emulate the audio circuit. I've been looking at the TIA schematic diagrams to try and work out the audio logic, but there's a weird circuit component that I've never seen before at almost every line intersection, particularly on the run of 5 vertical lines to the left of the 4 bit shift register on the right side of page 4, where the D1-4 latches and the output from the 4bit shift register meet. I've been eye balling this thing for a few days, and I can't imagine any component that would fit in those places. The spot i'm most concerned about is the D3-D4 latches, which appear to be another set of SR latches like the 4 bit shift register, where what appear to be Q and /Q are both wired to different lines via those funny circle components I refer to, and each of those lines meets another horizontal line at the top, each at more of the weird circle components. I have no idea how those signals meet at the top line, and what the resulting signal would look like... Can anyone tell me what the little circle line intersection component is meant to be? Also, does anyone have the illusive "TIA Hardware Reference Manual" that the Stella programmers guide refers to on numerous occasions? Google seems to turn up dry. If anyone has any insight, I'd love to hear it! Thanks!