Hi Curt,
this is good news and marvellous work you do there. A friend and I tried to implement the XL in a FPGA. But it is pretty much reverse engineering with a lot of traps and problems - since we both don't have access to a logic analyzer. This will be sped up considerably with your achievements. Maybe a VHDL definition could be genereated nearly automatically with the data you get...
I'm looking forward to hearing from your progress.
Elmar