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InsaneMultitasker last won the day on August 18 2019

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About InsaneMultitasker

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    River Patroller

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    TI-99/4A, Geneve, terminal emulation and BBSs, Anime ;)

    Employee of Cecure Electronics (1990s) where I repaired and upgraded Myarc & TI hardware.

    Geneve librarian for Milwaukee Area TI User Group

    SysOp of HeatWave BBS, operating on real hardware at 38.4Kbps. See signature for current Telnet address.

    Author of S&T BBS Software and other TI/Geneve programs

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  1. The Geneve OS source code refers to a 1MB option that as best I can tell was going to be on the Geneve itself. Additionally, the entire range of pages from >00 to >7F is encoded to be classified as FAST RAM or 0-wait state, with routines written to test for the existence of page >40 as the determining factor. Is there something we've missed with the current hardware? Maybe another board was planned that could use SRAM in place of DRAM?
  2. Might take a few seconds to get used to a clean bootup I have to focus on a work task the rest of the week so I'll merge your changes into my build Friday evening and will send you the memory routine MANAGE2S/MANAGE2T files for the ram detection changes at that time. Also, see my PM about IBMGRF and the video powerup routines. The only 'unknown' right now is whether or not any other tables, such as blink attributes, overlap the high characters. The char definition should be fixable with a call to XOP >28 upon exit to the OS, though I have to wonder if the SET video mode XOP is supposed to reset the characters along with the registers. Lastly, I have a few items to complete in the DSR code before I can modify EXEC to match GPL; I also need to figure out what I did with my PLAYE source.
  3. I'm thinking you are right in that it wasn't implemented, as I seem to recall Tony and others using "CLS" a lot in their batch files, probably for this very reason. I have to imagine that adding the @ functionality would be relatively simple. I'll note it for the next time I'm in HCLIS unless you decide to poke at it; I'm guessing it would be a matter of checking the first character of a line for "@" and if in batch file mode, set a flag to disable the echo for that command/line, update the starting position of the input line +1, and let the interpreter at the remaining characters.
  4. Lookin' good. Is it normal for the CLI to display ECHO OFF ? I only noticed because of the screenshot.
  5. we might need to create or necro a SID topic soon... Quick update: MDOS 7.xx now detects pages >C0-E7 as 'slow' ram per the earlier post and 384k topic.
  6. Interesting, I never used glue to secure the sockets. Thin tie-wraps were the practice by the time I started to install the modification. In many installations, the socket pin is bent to 90 degrees and a wire is soldered to it, then connected elsewhere on the board. So yes, if you remove the SIP from the bottom socket, that should be fine. You do NOT want the "bent" pins to touch the socket below. At times the wire was wrapped around the socket lead then bent >95 degrees, melted slightly into the socket housing, to stop the lead from being straightened. Removing the wipe was not an option as that would not allow reverting to standard 28-pin SRAM at a future date.
  7. Reminder to adjust memory identification per recent (and past) testing:
  8. The ROM speed is interesting as at one time there was documentation stating it was 0-wait state. I will correct the OS memory test to count pages C0-E7 as 1-wait slow RAM @Shift838 -nice board and implementation!
  9. Would you have time and desire to create a test program to validate the wait state/speed on real hardware? I would like to change the OS memory identification routine to flag pages C0-E7 as SLOW ram if in fact the wait state is inserted. The OS presently treats the pages as FAST ram.
  10. I should also mention that I don't recall if anyone confirmed the test results on real hardware.
  11. Address lines are picked up from the board and decoded. See Fabrice's website for the cleanest instructions and wiring information. Some time ago I believe that you proved, based on timing, that pages C0-E7 (those outside of the usual 64K SRMA) were not truly fast ram as previously thought.
  12. Whew. I thought my board said 'SID Blaster', maybe it was an early run. I don't have the card any longer. For Geneve reference I am fairly certain that the player maps >BA into the >4000 space mapper address at the start of the program. Then for both the TI and Geneve, the IO routine scans for WDS, IDE, and SCS devices to cache an appropriate entry point. I don't recall how (or if?) this is documented in the user guide. I have the source if changes are needed in the future.
  13. Perhaps. I have documentation referring to it as SID Blaster from when Marc, Ernie, and I worked on software development. I suppose the name changed at some point. @Ksarul?
  14. It cannot. These are allowed CRU addresses within the Geneve OS framework as it is more restrictive than the /4A.
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