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nichtsnutz

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Posts posted by nichtsnutz

  1. Posted

    Hello RevEng,

     

    thank you for your interest , I have attached the lpf file.You must remove the TXT ending.

     

    You will have to install the logicport software and run it in demo mode.

    There you can zoom and measure things.The logicport software is very easy and effective to use.

     

    I think the game was Pole Position 2 , but I can not guarantee it , it is too long back !

     

     

    Greetings ,

    vassilis

     

     

    MARIA_DL4_SHORT_2.LPF.TXT

  2. Posted

    Hello all,

     

    good projects are going on here on the 7800 section !

     

    I am reading since some weeks again here , and I could contribute a bit to the discossion.Long time ago I had taken some logic traces

    from the Maria chip.Here I have a trace of a DL4 fetch.

    You can see how HALT is going low (A) , two 4 bytes Display Lists are fetched together with their data , and the last DL4.

    After that HALT goes again high and the cpu continous the work at $D065.

     

    I unfortunately have not the VC7800 setup ready to take more traces.I would have to do a lot of work to be able to take good traces , but

    I plan to come back to it (very) slowly...

     

    Greetings,

    vassilis

     

    post-26516-0-82464500-1399299425_thumb.png

    • Like 2

  3. Posted

    Hello Kevtris,

     

    thank you for your answer.

     

    Some years ago, I had done some measurements of the frame timing for PAL here

    http://atariage.com/forums/topic/166451-pal-frame-timing/?do=findComment&comment=2057088

    and I got horizontal : 454 clocks @ 7,09MHz and 313 lines.

    PAL has normally 312,5 Lines per field and normally this is rounded down to 312 lines per frame,

    but they have done 313.

    So I think, they have done the same for NTSC.

     

    Maybe you can tell if the NTSC maria also is doing 454 clocks per line ?

    I suggest this,as I think that they only changed the vertical part of the maria chip

    and the color generation when doing the PAL chip.

     

    Many success with your project!

     

    Greetings,

    vassilis

  4. Posted

    Hello kevtris,

     

    in another thread that I do not find right now, Curt had posted a chip picture of the maria chip

    that he had recovered from the original netlist from the tapes.

    Unfortunately he has not made the data available public.

    May I ask where do you have the schematics from and are they at gate level ?

    Is the schematic of the maria chip available for free download ?

     

    Greetings,

    vasilis

  5. Posted

    Hello all,

     

    @jonny:I have bought them at: http://www.littlediode.com/components/home.php

    Not very cheap but the chips are in new condition.I think they are NOS (New Old Stock).

    I have not tried them out,but I have some free time until the weekend and hope to be able

    to do some register access...

    I had made an error in my last posting,the OPAs are the NJM4556AD and NJM4558AD.

     

    @philipj:Thank you for your opinion.I have searched a bit more and also found the

    FB-01 FM sound generator.The DX series keyboards are nice,but I can not play piano :-\

    I will search and take a look at them,also I have to learn more about the MIDI technic and protocoll.

     

    I have also found an "Arduino FM-SynthYM2151Shield" on youtube.The creator of this has also

    written a library " http://www.ooishoo.org/ym2151shield/ym2151library " to access the chip,so

    this maybe can also be used for experimenting.

     

    Greetings,

    Vassilis

  6. Posted

    Hello all,

     

    although I am not a musician,I am interested in the YM2151 from a technical point of view.Many registers to experiment with.

    I would like to add that the YAMAHA CX5M MSX computer had an extension with MIDI/KEYBOARD and a YM2151 stereo output.You can

    find things about it here: http://www.cx5m.net/techn.htm and here: http://home.online.no/~eiriklie/CX5MFAQ.html#midiaccess

    for example.The roms of the extension are also available and can be used with the bluemsx emulator (but without music!).

    The SFG-05 rom has 46 Programmed Instruments.It is not difficult to find them in the rom ($3680..$3F80) but I have not

    found out the format of the data except for the instrument name.Some Z80 disassembly has to be done,but it is not strait forward.

    They make heavy use of IRQs in IM1 and IM2 and I think they also use dynamic jump tables.It is not easy but with the breakpoint feature

    of the emulator some things can be found...

    This could be some starting point to have some data to play with.The service manuals of the CX5M are also available online.

    They also never poll the YM2151 directly,it is somehow in all this IRQ handling! But they also have code that writes addr and data

    in the registers without waiting.Maybe this is depending on the register that is written to.I unfortunately do not own one CX5M but

    bought a YM2151/YM3012 and NJM4456 to try to tinker a bit.The CX5M manuals have the circuit diagrams inside.

     

    I am also interested in the implementation inside the XM:

     

    - What will be the operating frequency of the YM ? (YAMAHA recommends 3,5795MHz)

    - The YM has two visible register,where will they be in the address range ?

    - Will the YM use IRQs ? if so will they be shared with the pokey ?

     

    - Will the XM use the YM3012 (stereo) or the YM3014 (mono) D/A converter ?

    - Will it have separate stereo outputs (if stereo) or will it mixed onto the audio pin of the cart ?

     

    Thank you for reading and your opinion,

    Vassilis

  8. Posted · Edited by nichtsnutz

    Hello all,

     

    thank you Rybags and candle for the reply.I have thought that you will have to do some synchronization because of the delays.Thank you for sharing the code.Also thank you Rybags for the explanation,this seems logical.I had also measured some of the behaviour you explained also.I think the best way to really understand the GTIA would be to connect it to an external circuit.

    Anyway,the posibilities with at runtime loadable hardware would be big with or without GTIA emulation!

     

    Greetings,

    Vassilis

  9. Posted

    Hello candle,

     

    although I do not own a VBXE I find the posibilities that this hardware has very nice! If the core developement is going to be opened I would think about to also order one.May I ask if you would like to explain a little bit more the clock distribution on the VBXE ? Also the generation of the CSYNC ?

    I took a quick look at the VBXE2 schematics and I think as follow:

     

    - 14.1875MHz are output from the Atmel and go to the VBXE2 as a main clock.

    - The 3.5MHz from the LS393 divider replace the GTIA main clock,so all things are synchronous.

    - GTIA outputs FPHI0 to the ANTIC that is also routid to the FPGA.

    - The ANTIC outputs PHI0 as the CPU clock and this is also routed to the FPGA,also PHI2 from the cpu.

    - ...

     

    I do not see any CSYNC output out of the FPGA,but the Atmel has one CSYNC signal.Is the Atmel generating the CSYNC or

    is it taken from the original GTIA ?

     

    The PCNT signal in you VHDL code seems to count 14.1875MHz / 8 = 1.77MHz so you have 8 cycles for every CPU cycle to synchronize on ?

     

     

    I an sorry if I ask to much,I am interrested in the hardware.I had done some timing analysing on the ANTIC some time ago,but I do not think this would be interresting for the most of you here but I definitely would like to see the whole XL on a DE0/1 or a Xilinx eval board,but this is hard work to do to get all the timing right.At the time I have the XL not connected because I mess around with my VC7800 trying to reverse some MARIA timings...

     

    Greetings,

    Vassilis

     

    PS: The image shows an exerpt from the ANTIC ANx timing.The ANx can be sampled with the falling_edge of the FPHI signal.I think ANTIC outputs the ANx with the rising_edge...

    post-26516-128169621713_thumb.png

  10. Posted

    Hello all,

     

    may I ask what chip fits into the 68p PLCC socket? Is it an CPLD/FPGA ? Is it from Altera/Xilinx/Atmel/Lattice ...

     

    I also find this a very interesting project and I would like to read more details about the implementation,

    like the mapper modes,etc...

    Is it intended to make more details public or will this details be only available to game developers?

     

    Greetings,

    Vassilis

  11. Posted

    Hello doppel,

     

    Hmmmm...well things seem to be slightly different on the PAL 7800. When I referred to "color clocks" I was referring to the 3.58 Mhz clock used both for the NTSC chroma sub-carrier and the TIA timing. I'm not at all clear on how the external PAL chroma clock affects the output versus NTSC.

     

    Ok,I understand now,I have to say that I do not know for sure what a "color clock" is.I'm sorry my false! On the atari XL I think the GTIA clock is the color clock!?

     

     

    I never actually said the CPU clock was fixed, in fact I don't recall mentioning the CPU clock cycles at all. But the figure of 114 (or is 113 or 113.5 now, these damn figures keep changing) should apply to the maximum speed of 1.79 MHz, naturally going down for any cycles spent accessing slow RAM or the TIA.

     

    I think the same,with the CPU speed changing there will be always a different number of cycles.

     

     

    It was you as I recall that mentioned there being 227 PAL color clocks per scanline (which, as I stated in the previous post, corresponds precisely to 454 MARIA clocks). How the external PAL clock of 4.43 MHz affects things, again, I have no clue, since I don't have any PAL hardware or any way of measuring any of this stuff.

     

    I am sorry for that,I have used the term without knowing what it really means and I have just used it because others also use it :roll: .On the PAL MARIA the PIN_3 has a different function from the NTSC MARIA because PAL needs this 4.433 "color clock"! This is only needed for the color coding and I think is not used for something else.

     

     

    And as far as to why the hardware in a PAL 7800 would be clocked different from an NTSC 7800, I also have no idea. I'm gonna go ahead and stop right here, since I'm obviously not a hardware person...

     

     

    I only have a PAL machine and maybe they have done things different with NTSC.I have also no definitive answer!

     

    I have measured many other things like the DLL fetch transfers,DMA Startup/Shutdown,and I must say that the more I measure the more I am confused.It is really not easy stuff,the ones who design such things are real experts.I will take a rest for some days,maybe one day things will clean up...

     

     

    <throws his hands up in frustration and walks away>

     

    I am sorry I have not wanted that,I respect your opinion! My measurements were for PAL and yours for NTSC! Also my englisch is "machine" like and reads "hard" because I am no native speaker! But I do not want to blame anyone.I am sorry if it feels so.

     

    :)

     

    Greetings,

    Vassilis

  12. Posted

    Hello doppel,

     

    This should hopefully clear everything up.

    This confuses me a bit more :?

     

    The MARIA screen layout shown on page.13 has one mistake.The number of clocks per line should be 454 and not 452.All other horizontal timings are the same with the ones I have measured.(At least for PAL.)

     

    I also do not understand what you mean with "color clock".For me one PAL color clock is one cycle of the 4.4336...MHz clock on MARIA_PIN_3 that is used for the PAL color burst.This is only used for the color coding of the chroma signal that is output on the COLOR pin.It is not used for anything else.

     

    The CPU can be clocked with two different frequencies either 14.1875/8=1.773MHz or 14.1875/12=1.182MHz so there is no fixed number of CPU cycles per scanline.

     

    MARIA is clocked by 14.1875MHz and this is internally divided by two to get 7.09MHz.The 7.09MHz (140,9ns) clock is used internally for all the raster timing.

    I have attached the measurment.Line length from A-E = 64us.

     

    Now, 93 + 39 = 132 border/offscreen MARIA clocks. 132 * 2 = 66 color clocks. Couple that with 320 pixels * 2 and that gives us 160 color clocks, giving us 226 total color clocks, which corresponds to 452 MARIA clocks more precisely. 227 isn't too far off, which would correspond precisely to 454, or roughly to 452, give or take an extra clock somewhere.

     

    :?

    What should this 226-227 color clocks mean? This is not a PAL Atari XL with 3.54MHz fixed clocking where the CPU clock is the half of it and fixed!

     

    Greetings,

    Vassilis

    post-26516-128039316716_thumb.png

  14. Posted

    Hello Rybags,

     

    yes,I think that the CPU is offset by half cycle on each line.I had also recorded the CPU clock that gets out of MARIA and I could see that every time I had triggered,it was shifted with respect to the csync.I could not get a stable timing between the cpu clock edge and the csync edge,but I have to look at this again.

    Vertical blank is on PAL 21 lines that leaves 313-21=292 lines for the image.I think using 192 lines is the standard on the 7800.

     

    Unfortunately the small logic analyzer that I own is not able to record a whole video line with all the maria signals,so I am trying to build an external trigger logic based on decoding the maria csync and counting lines.If I succeed with this I could also trigger the position of the DMA transfers.This could be interesting for emulator writers getting the cycle counts exact.But doing this is not so easy as it sounds...

     

    Greetings,

    Vassilis

  15. Posted

    Hello all,

     

    I had posted some timing diagrams in the other thread "PAL frame timing" and I can say from what I have measured that the PAL-MARIA makes 454 Clocks per line.With a sampling rate of 200MHz I get exactly 64us (+/- 5ns) accuracy and that is (14.1875 / 2) * 64us = 454 Clocks per line.This is 227 PAL color clocks or 113.5 CPU Clocks per line.The PAL FRAME is 313 lines.

     

    I have no NTSC VC7800 but I think that they have taken the same horizontal timing for both standards to reduce the hardware cost.The nominal line length of NTSC is 63.55us * 7.16MHz = 455 Clocks,this is one more than in PAL,so I think they just took also 454 Clocks per line for NTSC to have the same DMA hardware for both systems.They had only to change the vertical counter that is perhaps easier than changing the whole DMA logic for 1 clock more per line !!! So the NTSC line length drops to 454 / 7.16 = 63,4us that should be tolerable from the analog TV of that time.

     

    Greetings,

    Vassilis

  16. Posted

    Hello all,

     

    this is my first post here although I read atariage for two years now,so I first would like to thank the people behind this nice forum and also those who contributed so much to the 8 bit atari systems.In my profile I have written a little about my interests,so read there if you like.

    Ok,now to topic.

    I am primary interested in the hardware of the ataris and I have taken some timings of the

    PAL MARIA sync and blank signals.What the documentation states is right (454 Clocks per line and 313 lines per frame for PAL).Although I am a bit confused,because 454 Clocks / 4 = 113.5 cpu clocks per line,so at least on PAL there is no integer cpu clocks per line when I assume thar the cpu runs with 1.77MHz.(No switch to the slow mode)

    Anyway,if someone is interesed I have also attached the Logicport files,you can open them with their software to measure things.

     

    Bye,

    Vassilis

    post-26516-127990661923_thumb.png

    LogicportFiles.zip

    post-26516-12799069878_thumb.png

    post-26516-127990699038_thumb.png

    • Like 1
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