AtariGeezer

It works good You'll need to do your homework too....

Update on my progress: Finished wiring up my v3 board 6 days ago and since then I have been doing my Homework searching docs and code for all the SIO commands pertaining to the 850. My new sketch with 850 and Modem emulation is progressing quite nicely From the disassembly of code from the PRC handler and Bob Puff's programs, I have a good understand of the Code Relocation methods, so writing a new bootstrap shouldn't be too difficult

These Disks arrived today Thanks again Ryan 👍 Will test the CP/M disk soon...

Years ago when zaxon made the Side1 Carts, he didn't install the JTAG header either and just programmed them with wires sitting in the thru-holes. I ended up buying 10 headers on ebay for dirt cheap to install in those...

Hmmm, I guess it is: esp8266-is-5v-tolerant-after-all

I have a XF551 hooked up that way and it does work

Refresh? How so???

I've touched on thus subject before: https://atariage.com/forums/topic/262518-sio-wifi-modem-with-esp8266/?do=findComment&comment=4371533

These are the notes I took from the hardware manual: IHMEDIATE Sequence: ---+ +----------------------------------- COMMAND- | | +--------+ +------+ DATA OUT | cmnd | ----+frame +------------------------------------ +-+ +-+ DATA IN | | | | ---------------+ +----------//-----+ +---------- ACK CMPL || || | | | t0 t1 t2 t5 DATA SEND Sequence: ---+ +----------------------------------- COMMAND- | | +--------+ +------+ +---//---+ DATA OUT | cmnd | | data | ----+frame +------//--+ frame +---------------- +-+ +-+ +-+ DATA IN | | | | | | ---------------+ +-----------------+ +--//--+ +- ACK ACK CMPL || || | | | | | | | t0 t1 t2 t3 t4 t5 DATA RECEIVE Sequence: ---+ +------------------------------------ COMMAND- | | +--------+ +------+ DATA OUT | cmnd | ----+frame +------------------------------------- +-+ +-+ +----//----+ DATA IN | | | | | data | ----------------+ +--//--+ +-+ frame +-------- ACK CMPL || || | | | t0 t1 t2 t5 The computer generates a delay (tO) between the lowering of COMMAND- and the transmission of the first byte of the command frame. computer tO (min) = 750 microsec. computer tO (max) = 1600 microsec. peripheral tO (min) = ?? peripheral tO (max) = ?? The computer generates a delay (tl) between the transmission of the last bit of the command frame and the raising of the COMMAND- line. computer tl (min) = 650 microsec. computer tl (max) = 950 microsec. peripheral tl (min) = ?? peripheral tl (max) = ?? The peripheral generates a delay (t2) between the raising of COMMAND- and the transmission of the ACK byte by the peripheral. computer t2 (min) = O microsec. computer t2 (max) = 16 msec. peripheral t2 (min) = ?? peripheral t2 (max) = ?? The computer generates a delay (t3) between the receipt of the last bit of the ACK byte and the transmission of the first bit of the data frame by the computer. computer t3 (min) = 1000 microsec. computer t3 (max) = 1800 microsec. peripheral t3 (min> = ?? peripheral t3 <max> = ?? The peripheral generates a delay (t4) between the transmission of the last bit of the data frame and the receipt of the first bit of the ACK byte by the computer. computer t4 (min) = 850 microsec. computer t4 (max) = 16 msec. peripheral t4 (min) = ?? peripheral t4 (max) = ?? The Peripheral generates a delay (t5) between the the receipt of the last bit of the ACK byte and the first bit of the COMPLETE byte by the computer. computer t5 (min) = 250 microsec. computer t5 (max) = 255 sec. (handler-dependent) peripheral t5 (min) = ?? peripheral t5 (max) = N/A Communication First, the computer sets the COMMAND line low at the SIO connector. Then sends the Command Frame (4 bytes + checksum) Then waits for a response (1 byte without a checksum): $41 (A) = Acknowledge, the Command is valid and will be executed. $4E (N) = Negative, the Command is invalid. If the device responds with a "N" (NAK), the transfer is aborted. Otherwise ("A") and the Data Frame is transferred with the checksum. Now the computer waits for a final acknowledge (1 Byte without a checksum): $43 (C) = Complete, operation completed successfully. $45 (E) = an Error has occurred

I would think there is more interest out there. maybe a x-mas rush is looming

Except for the dreamblaster s2, the rest of my parts orders will arrive this week. So hopefully I can start my 1st build this weekend @MacRorie, How many of these boards are out there???

Try this: In setup() Add pinMode(PIN_CMD, INPUT); change attachInterrupt(digitalPinToInterrupt(PIN_CMD), sio_cmd_change, CHANGE); to attachInterrupt(digitalPinToInterrupt(PIN_CMD), sio_cmd_change, RISING);

esp8266-12e's are only $7... https://www.ebay.com/itm/232384303034

Do you want to sell them?

Interested

Will do

Yep, I think I'll make a new sketch that is SIO driven setting a GPIO to act on interrupts generated by COMMAND. Basically an enhanced R: device...

This is what my v3 board looks like, just need to wire it up now. And it's schematic.

What do you consider is a reasonably-priced Atari 800??? I have a couple of my spares to sell soon...

Incognito used to have a home there...

Yep, and the seller won't sell it by itself...' Might be the one from Steve Stuntz...

Do you still have the sketch for that?

If anyone here can program a 8040 MCU, I don't see why not...

Yep, my objective is to first develop a working R: Handler supporting RTS / CTS flow control and Carrier Detect / Drop, RING Indicator / Count, plus testing a new Amodem using that. Then I'll make the revised board dropping the 74LS00's. A new Atari-Zimodem firmware should be debugged by then...

This is the layout I'll use. The 2 level shifters mount right under the NodeMCU And the updated schematic