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jens-eike

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Everything posted by jens-eike

  1. My Geneve has heat sinks on the regulators, hence it cannot use the case - but the back part of the case helps with the correct orientation and seating. When you close the PEBox's lid, the foam will press the Geneve into its slot. As you can see, I've done it with the Geneve and HFDC. The box is upright (drives on top).
  2. http://www.famkoplien.de/henry/TI99/
  3. Not a BwG card: see this picture: https://www.s-n-u-g.de/bwg/index_fr.php The TMS9901 is typically a sign of a CorComp card. My CorComp card has a 1773 controller, but I have seen the 2793 mentioned (on whtech?), they are software compatible.
  4. There is no simple PAL video cable, the console has outputs for YUV (aka YCbCr/YPbPr?) component signals. Some modern TVs can take these directly (my LG 42LF65 did). Otherwise, the PAL modulator mod gives you the composite signal (slightly better quality than from US NTSC consoles), or you could use the SCART/Peritel RGB modulator (mostly sold in France) for the best quality picture. A schematic for an RGB-enoder was in the November 1988 issue of the ChicagoTImes, I built this twice, good stable picture. Then there are upgrades based on the 9938 VDP ("80column cards"), or the F18A for VGA output.
  5. With proper address decoding, only one CRU device is active at any time - so this shouldn't be an issue. The 9901 in the console isn't fully decoded, so keep out of it's address range! http://www.mainbyte.com/ti99/schematic/schematics.html has several schematics, the FDC card has the '251 connected directly to CRUIN.
  6. Since CSYNC comprises high frequency signals in the range 15.6kHz, I would connect it to HSYNC first. VSYNC is the 50/60Hz frame signal, and you would miss the line synchronization if using this input only. If this fails, try parallel connection to H and VSYNC If that fails, too, try a circuit with a LM1881 sync separator (8-pin IC and some passives)
  7. Wouldn't that compare R0 to 2 (immediate value), C R0,R2 compares two registers. The assembler option "R" does an operation like "R2 EQU 2"
  8. From the docs (tiif.txt): "Since Windows XP and newer doesn't allow direct access to the IO-port of the LPT-card, a system kernel driver is required. I decided to use TVicPort (http://entechtaiwan.com/dev/port/index.shtm) which is free for non commercial use. This combination was successfully tested on a Windows 10 32 Bit PC with an onboard LPT-port and a Windows 10 64 Bit PC with a PCIe LPT-port."
  9. just found a current version: https://groups.google.com/forum/#!topic/comp.sys.ti/_xbwmWs5gXY http://pengels.bplaced.net/index.php/tiif
  10. In comp.sys.ti was a post about a new version of the PC-IF: https://groups.google.com/forum/#!topic/comp.sys.ti/WT3qdYD1tZE the link to acg-bonn.dyndns.org/~en/downloads/files/tiif.zip still works, the file contains schematics and software from DOS to WIN32
  11. How about MOVB *R1,*R1 ? Still testing for 0 without using any extra register, but slower (about 2 cycles).
  12. My old LCD-TV (LG 42LF65) took the TI signals on YPbPr input - best possible quality without any modulator! The RGB circuit in "Chicago TImes" (ca. 11/1986) is quite easy, only a handful of transistors and passives. That is my favourite, if you have a RGB-capable Scart input.
  13. Another option would be the Mini Memory cartridge, it contains 4K RAM and the Line-By-Line-Assembler cassette tape. There is no need for a PEB or other expansion hardware, just a cassette recorder and the cartridge (with tape).
  14. Dear fellow TI'ers, the TI-Club Errorfree invites you to the international TI-Treff 2016. The 31st international TI Treff will be held from September 30th to October 2nd in Denmark. The location is the Hotel Svalen in Hedehusene near Copenhagen. The Treff starts on Friday and goes to Sunday afternoon. Friday is for set-up of the computers, and we'll have dinner at the "Porterhouse" in the city. Saturday is for demonstrations of hard- and software, talking & exchange of ideas, auction, club presidents' conference and a dinner, afterwards computing till early morning (if you desire...). Sunday is for more sharing of experiences and packing, or a tour of Copenhagen. There is a conference room in the hotel at our disposal, rent (and dinner) is included in the room price, so we'll take a fee from "external" visitors. At the Saturday dinner, this years Edgar Mauk award winners will be announced. Prices: A room is DKK 2390 for two nights (approx. EUR 319), including the meeting room and dinner. Since we got allotted some rooms, please book (as soon as possible) your room through: Jens-Eike Hartwig, phone +49-461-9787778 (best between 20:00 and midnight CEST) or je_hartwig(at)yahoo(dot)com The address: Hotel Svalen Roskildevej 333 DK-2640 Hedehusene Please do not book through the hotel or booking websites, since the rooms are pre-booked! More information about Copenhagen: http://www.visitcopenhagen.com
  15. The TI-99/4 was to have a TMS-9985 CPU, according to it's specifications, the internal RAM was at >8300. Later TI designed the TMS-9995, again with internal RAM - but why at >F000 and not at >FF00 to be contiguous with the NMI/LOAD vector at >FFFC...??? Internals about TI CPU and VDP design: http://spatula-city.org/~im14u2c/vdp-99xx/
  16. That is normal, if it is NTSC - ringing of the video signal at sharp edges (contrasts) gives all kinds of colorful effects :-(
  17. Remove the small sticker from the write protect notch Seriuosly, check your firmware - old versions were read only for TI formats... http://hxc2001.com/download/floppy_drive_emulator/index.html According to http://hxc2001.com/download/floppy_drive_emulator/sd_hxc_floppy_emulator_firmware_release_notes.txt firmwares above 1.8.2.24 have fewer problems with floppy writes.
  18. There is some info on Tomy Tutor (Pyuuta) hardware here: http://www.floodgap.com/retrobits/tomy/hardware.html More detailed schematics: http://www43.tok2.com/home/cmpslv/Pyuuta/EnrPt.htm (Japanese text)
  19. The Test program logic in the original post may have a flaw(?). When testing VDP-RAM and not taking into account the auto-incrementing of VDP addresses, that could give the above pattern. But then, it should give the same error on all locations...
  20. Look at Stuart's site: http://www.avjd51.dsl.pipex.com/tms99110_breadboard/tms99110_breadboard.htm
  21. The TMS991xx can add wait states to any operation (memory, internal, cru), so it should be possible to use the 9902. The 9901 can be replaced by '251 (input), '259 (output) and '348 (interrupt priority) TTL chips without speed penalty. Bonus: the TMS991xx can do parallel I/O for CRU addresses above >8000
  22. Another note: check your timing requirements. 100ns RAM could be too slow for worst-case operation. Consult the data book, from address stable to data in is much shorter than 330ns! According to my TMS9995 Data Manual (December 1984), page 56, the access time is 3/4*tc2-135 (3/4*333-135=114ns with a 12MHz clock, at 16MHz: 3/4*250-135=52ns). Subtract any delay from TTL buffers or decoders like 74LS244 (30ns) or 74LS138 (39ns) and a '245 (40ns) buffering the data bus (maximum values from The TTL Data Book 1987). As you can see, LS-TTL logic is not going to make it, that's why TI invented the automatic first wait-state. Using faster logic (ALS/F/ACT...) and really fast RAM (628512 is available in 55ns) can do the trick.
  23. That is just what the Cortex does: copying the content from the EPROMs to RAM, then running the OS from RAM. Great idea, you can modify any BASIC command :-) What is wrong with ROM, if you don't have to worry about slow access speed...
  24. Actually, both CPUs run on 12MHz. The 9995 has an internal clock generator deriving it's microcycles from the crystal, externally, all we see is the memory cycle and the -phi clock output. The 9900 gets four clock phases from it's TIM9904(A), derived from a 12MHz crystal (older TIM9904 use a 48MHz crystal, most 99/4 have these). Peripheral chips like the TMS9902 use only one phase of the clock signal, so a 3MHz signal -phi3 controls most of the timing. Note: -phi3 is one fourth of the clock signals, so it's duty cycle is about 80ns active (low) and ~250ns inactive (high) (+/- rise and fall times). Early 9901s had a problem with the 50% duty cycle of the 9995, so TI produced chips marked TMS9901-95 and TMS9902-95 for compatibility with the 9995.
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