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jens-eike

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Posts posted by jens-eike

  2. Posted

    Hej Rasmus,
    the PCB is from German TI-Revue. Two EPROMs seem to be stacked in the GROM area, ther is provision for cartridge ROM at the empty 28-pin solder pad area, this can be modified to accept an 8K RAM chip. Back in the days I modified this PCB to a battery backed GRAM device with bank switching to run Extended Basic (my home made GRAM Kracker).

    post-28823-0-38614400-1379754359_thumb.jpg

  3. Posted

     

    I cannot really imagine why SWPB (a particularly simple command) should take that many cycles. My guess is that this is an intentional delay, just related to the issue with delays when accessing slow devices like the VDP. With this slowed down execution you could stay with the common MOVB/SWPB/MOVB sequence when setting the address without changing the source code. (Just a wild guess, yes.)

     

    Another wild guess: is SWPB implemented as a (circular) shift? That could explain the sloooooow execution, even on the 9995.

  4. Posted

    I agree about the TMS9918A, it was an odd choice to put into their new console... to be fair, though, it WAS a prototype. They were probably just putting what they had available in it.

     

    The V9938 chips were made by Yamaha and introduced three years after TI left the home computer market. I'd be curious to know if TI had been planning to make such a chip eventually, or if was all Yamaha's ideas... Wikipedia offers no insight.

     

    Adamantyr

     

    Look for the TMS9228, it is the missing link with many features of the 9938 designed by TI. Most video modes like 80*24, 512 color palette, 256*210 bitmap etc were planned for this chip. I read a full preliminary data book once, this link shows only an excerpt:

     

    http://www.datasheetarchive.com/TMS9228-datasheet.html

     

    The 99/8 has a TMS 9118 VDP, the newer design with only two TMS4416 RAM chips (16k*4bit each).

  6. Posted

    This datasheet: http://ww1.microchip.com/downloads/en/DeviceDoc/11173G.pdf

    states an erase cycle time of 40minutes, that seems rather long, TI's TMS27C512 was specified with an erase time of 21 min (MOS Memory Data Book 1991), my experience is 15min should suffice (blank test OK).

     

    Oops, yes the 29C512 is 32pin, my bad.

     

    Same offer, if you send me the *.bin file, I can program the chip for you, Flensburg is probably closer thus cheaper and faster mail.

  7. Posted

    If you want to keep it with the TI-99: the ASCSI card allows to program Flash-EEPROMs with the DSR-Loader program:

    http://home.arcor.de/system-ninety-nine-user-group/util/dsrldr3_e.pdf (omit _e for German version)

     

    What size EEPROMs do you mean, 8k*8 is 8k bytes or 64 kbit EPROM: 27©64, EEPROM: 28C64 (see Thierry's page about EEPROMs), 64kbyte = 64k*8 = 512kbit is 27C512 (EPROM) or 29C512 (Flash-EEPROM, Atmel AT29C512 is usable in ASCSI!). I am not aware of an EEPROM of this size, but a 32kbyte version is available: 28C256.

     

    All of the above chips come in 28-pin packages and should be usable on the cartridge board, but check for connection of the -WE signal, if it is connected to the E(E)PROM, it could cause trouble (writing to the EEPROM while changing banks).

     

    Jens-Eike

  9. Posted

    the modification of the modulator is described at: http://www.ti99.com/ti99r1.htm

     

    No, you probably have to make your own. I have an intermediate solution for my 99/4A, where I use the PAL antenna signal modulator, but not all the way. Instead of using the RF antenna output, I've tapped into the modulator and routed the color video and sound signals out separately. These I've then routed to the my monitor's composite video and sound inputs, respectively. Gives a better picture than RF, even if it's inferior to RGB.

     

    Haven't tried this on any modern flat TV unit.

  10. Posted

    The 6-pin output has Y, R-Y (Pr) and B-Y (Pb) signals. Y can be used as black/white output, but color needs serious encoding (see the color circuit in the Powetran Cortex schematics at powertrancortex.com. Modern TVs with component input (YPbPr) can display the color differential signal directly, and witout the rainbow color distortion seen on NTSC consoles :-)

    To answer your question: there is no such thing as 6-pin A/V cables (for the TI).

    • Like 1

  14. Posted · Edited by jens-eike

    Been watching and liking !!!

     

    A question..

     

    If the 9995 only has 8 data lines then how in the hell does it doe word operations ?

     

    like the TI-99/4A: sequentially. The TMS9995 reads the bytes in logical order, address 0 before 1, while the TI-99 reads the low byte first. (that is the reason why Thierry's cards have a TI/Geneve switch for byte order)

    benefit: the 9995 can read or write single bytes, while the 9900 reads a word and writes back the word with the modified byte (the dreaded read-before-write that slows everything down in our TI)

  15. Posted · Edited by jens-eike

    Stuart,

     

    I see you plan to run the 9995 at 12mhz. I've ordered 100ns EPROMS. I think 100ns is too slow for 12mhz... so there'll be wait states I think.

     

    The 12MHz are divided by 4 to 3 MHz, resulting in a 330ns memory cycle. Depending on the decoding logic, 100ns should be fast enough. The TMS9995 data book gives timing diagrams with necessary setup times. (I am going for 45ns EPROMS for a 99105 board w/ 167ns memory cycle)

     

    edit: just found the timing diagram, it has the access time t(acc)=3/4*t(c2)-135 = 3/4*333-135 = 115ns, so your memory allows 15ns for decoding.

  16. Posted

     

    Question re the Rom and RAM chip select signals.

     

    You take A0 and invert it and AND it with /MEMEN

     

    I wanted to know, could you not also derive RAM_CE from ROM_CE by simply running ROM_CE through an '04 inverter, thus saving an AND gate?

     

     

    The 'LS32 is an OR-gate, if either -Memen OR A0 is high, -ROM_CE is high (EPROM inactive). This is not the -RAM_CE select condition, as -MEMEN still needs to be low, else the ram could write false data at CRU accesses.

    An OR-gate is an AND for negative logic: if both -MEMEN AND A0 are low, the select is low (memory access at >0000->7FFF), for >8000->FFFF, invert A0 as in the schematics.

     

    Happy new year!

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