Stuart

To answer my own question … http://www.whtech.com/ti/atkeyb.html

So what does it do and how is it fitted? Is it soldered on top of the processor? You'd need to cut away the metal shielding?

I've got a couple of systems with the TMS9918 and they seem pretty tolerant of the load capacitor value. Just checked one board which uses a 33pF cap on one side of the crystal, and a fixed 22pF + 22pF variable cap in parallel on the other side of the crystal, and it's rock solid. VDP keeps in sync with the variable cap at each extreme end of adjustment. No video glitches if I probe round the crystal circuit with a damp finger. It's using an NDK crystal removed from a broken TI-99/4A. I'd suggest that the problem is *not* the load capacitors.

If you're talking about an I2C EEPROM, you can implement an I2C interface easily on a 9901 - I done one using the joystick port. http://www.stuartconner.me.uk/ti/ti.htm#i2c_interface https://learn.sparkfun.com/tutorials/reading-and-writing-serial-eeproms Edit: Ideally you'll need *three* unused pins on the 9901 to implement an I2C interface: one to drive the clock, one to output data, and another to input data - because once you programme a pin on the 9901 as an output, you can't use it again as an input unless you do a hard or soft reset of the 9901. You might be able to get away with doing a soft reset at the point where you want to switch between reading and writing the interface, depending on what happens to the clock output at the point you do the reset (will it float high or low, and what does the I2C interface expect on the clock output at that point?), and what other things are connected to the 9901.

Jim, the source for Parsec. That looks like one copy written in GPL, plus another copy written in assembler - is that correct? Or is it GPL *plus* various routines written in assembler?

http://www.stuartconner.me.uk/ti/ti.htm#i2c_interface

Is the licensing not based around the last party involved in the manufacturing process? It would have been TI if they were selling the 99/4A with the F18A already fitted, but in the current case, it's sounding like it all comes down to you. (And I feel for you - a right PITA that the F18A has got caught up in the licensing issue, but sounds lucky that you found out sooner rather than later.)

If one had a 'scrap' PEB, could you Velcro one of the removable lids to the bottom?

"I've put the circuit under a logic analyzer and can confirm that the chip itself is returning the 0xFF bytes. What's less clear is whether it's driving the bus at all, or the lines are just being pulled up by the CPLD." Could you put a 'weak' pull-down resistor on one of the data lines to tell if it's driving the bus, or if the line is just floating high?

Just to expand on what Ciro said above, it seems that the instructions supplied with the MiniMem cassette games say to load them using the EasyBug 'L' option, then to go back to the MiniMem start screen, select options 3,2 (RUN) and just press <Enter> for the program name, and the game starts. That doesn't work when loading the dumped data from disk - you need to specify the program name to run. To check the program name you need to enter, what you can often do is load the dump file into NotePad (assuming you’re using Windows), and look at the very end of the file – you’ll probably see a program name there (all uppercase, max 6 characters). For the Sneaky game, you can probably see the program name you need to enter from the line below. ÿŒ”‡”€”‡”Œ”…”Ÿ ÿ ¶­µª´¨³¿ Ÿ¿ßÿ KSCAN SNEAKYup

Some versions of TI Invaders had the cheat code as well. http://atariage.com/forums/topic/176730-ti-invaders/

First, you need the 32K memory to be available (that's where the CART_RAM program is loaded to). Load the program using the MINIMEM options 3, 1 (the MiniMem cartridge has an assembly loader similar to the E/A cartridge).

The QI power supply uses a switched mode design for the 12V supply rather than a simple regulator, so it produces less heat. Glad to hear it all works!

Well, there's this row of 8 toggle switches ....

The +12V regulator in the console power supply is a UA7812C which is rated at 1A. The console draws about 330mA from the +12V supply. Drawing another 400mA from the +12V supply is probably possible, but the regulator/heatsink are going to get pretty damned hot in their confined little space. Personally I'd hook the screen up to a separate external supply.

So why 10.7 MHz? That's also the frequency for the VDP, so are they driving both the CPU and VDP from the same crystal? Is running the CPU at this slower speed just a cost-cutting measure to save a separate 12 MHz crystal, or is there some benefit somewhere?

You've presumably seen that there's a load of TI990 docs on eBay at the moment? Just sayin' in case you've missed them somehow. You'd probably need to sell a body part to buy all of them though. Might be worth approaching the seller for a bulk buy if none or little of it sells.

The TIM9904/74LS362 are early versions and need a 48 MHz crystal. The later TIM9904A needs a 12 MHz crystal. So check the markings on the crystal and that will show which version of clock chip you need. The TMS9904ANL is definitely a Chinese knock-off. But some of them do actually work fine (in the short term at least).

What are you using the 2.9V for? It will measure as 2.9V if you measure it with a multimeter, but if you draw any appreciable current from it then it will upset the voltage.

Error codes first. I believe XB will give you error code 00, and plain TI BASIC will give you error code 50. So if you were previously testing with TI BASIC, there's no problem with what you're seeing. Try the test using the MiniMem cartridge, and see if you get the same results. In hex, what you're seeing through XB is >00, >83, >E0, >00, and >83E0 happens to be the first two bytes of the console ROM ...

You can also do some testing using the MiniMem cartridge, if you have one of those. I finally got round to putting some notes together for this: http://www.stuartconner.me.uk/ti/ti.htm#checking_disk_controller_card_dsr.

Did you look at the Ralph Molesworth "Introduction to Assembly Language ..." book (which you have listed in the Development Resources thread)? That's the book that made file I/O 'click' for me, and contains a good working example. Note that there's an error on page 82 - in the block of two lines near the centre of the page, the first line "LI R6,PAB+9" should be "LI R6,PABADR+9". I also have a scribbled note you need to execute those two lines (basically setting >8356) before *each and every* call to DSRLNK. Your question 2 - I believe all data transfers are through VDP RAM, you can't transfer directly from CPU RAM. So for saving a sequential file for example, you would copy a record from CPU RAM to VDP RAM, write the record to disk, transfer the next record from CPU RAM to VDP RAM, write to disk, and so on. Your question 3 - I don't believe GPL is involved (or has to be involved). Everything is done through DSRLNK calls. Here's a fairly simple example from my Internet Browser program, used to open the Favourites file and read it in line-by-line. ********************************************************************************** *Define PAB for disk access (loading the favourites file) for TI99EA3 and TI99CRT. ********************************************************************************** BUFADR EQU >1C00 VDP RAM address for record buffer. PABADR EQU >1D00 VDP RAM address for PAB. PAB BYTE >00 Op-code: Open. BYTE >14 File type: Sequential, Input, Variable, Display. DATA BUFADR Buffer address in VDP RAM. BYTE 80 Record length. BYTE 80 Character count. DATA >0000 Relative record number. BYTE >00 Cassette screen offset. BYTE 16 File descriptor length. TEXT 'DSK.BROWSER.FAVS' File descriptor. PABSP BYTE >01,>16 Program name length and program name for sub-program in Disk Controller DSR that * sets the number of file buffers. READ BYTE >02 Op-code for file operation. BYTE 0 Padding byte to restore even address. *Set number of disk files supported to 1 ("CALL FILES(1)") to move the disk controller reserved area in VDP RAM *from >37D7 (where it overlaps with the colour table and sprite generator table) to >3BE3 (where it only overlaps *with a part of the sprite generator table that we don't use anyway). ENDCONF LI R0,PABADR Copy PAB for sub-program to VDP RAM. LI R1,PABSP LI R2,2 BLWP @VMBW MOV R0,@>8356 Set up pointer to sub-program name length byte in VDP RAM. LI R0,>0100 Set number of disk files in the byte required by the sub-program. MOVB R0,@>834C BLWP @DSRLNK Call the sub-program. DATA 10 ================= *Handle display favourites key. MOV @CRCARDB,R12 Switch off serial interface on NanoPEB/RS-232 Card before using disk access. SBZ 0 LI R0,PABADR Copy PAB to VDP RAM. LI R1,PAB LI R2,26 BLWP @VMBW LI R6,PABADR+9 Set up pointer to file descriptor length byte in VDP RAM. MOV R6,@>8356 BLWP @DSRLNK Open the file. DATA 8 JNE MSSP190 Equal bit in status register will be set on DSR error. Jump if no error. BLWP @WRTCHRS Print DSR error message at bottom of screen. DATA 42*23 DATA MSG12 DATA 42 BL @UPDTSCR MOV @CRCARDB,R12 Switch serial interface on NanoPEB/RS-232 Card back on. SBO 0 B @MSSP00 Loop round and wait for next character from keyboard. MSSP190 MOVB @READ,R1 Change file op-code to 'Read'. LI R0,PABADR BLWP @VSBW LI R3,PGBUFF Address of page download buffer. MSSP191 MOV R6,@>8356 Restore pointer to file name. BLWP @DSRLNK Read data into buffer in VDP RAM. DATA 8 JNE MSSP192 Jump if no DSR error. * (A DSR error is expected at EOF. Any other error is ignored. File is closed * automatically when the EOF is reached.) MOVB @B00,*R3 Add end of page marker to page download buffer. CLR @DSPLYSC Reset a couple of flags to the default value so that newly loaded page is CLR @NOSCRLL displayed correctly. CLR @INTIMEO MOV @CRCARDB,R12 Switch serial interface on NanoPEB/RS-232 Card back on. SBO 0 B @RNDR Render page. MSSP192 LI R0,PABADR+5 Address of character count in PAB. BLWP @VSBR Read number of characters read into MSB of R1. SRL R1,8 Shift to LSB. MOV R1,R2 Copy characters read from VDP RAM buffer to page download buffer. LI R0,BUFADR MOV R3,R1 BLWP @VMBR A R2,R3 Update pointer in page download buffer. JMP MSSP191 Read next line from file.

That's a nice way of getting the code to run, Michael. When I've played around with this before, I found that the CALL PEEK command switched off the card DSR, but I can't reproduce that now. Re-enabling the card every interrupt would be a neat way around that. Edit: I've found what I done. If you CALL PEEK with the XB cartridge then the card DSR remains enabled. If you CALL PEEK using the E/A cartridge, the card DSR is switched off after the CALL. Strange.

Also take a look at http://atariage.com/forums/topic/273707-in-need-of-corcomp-fdc-pics/?p=3930964 if you want to do a deeper dive into the DSR.

What command are you typing at the console, and what error code is it returning?