Jump to content


+AtariAge Subscriber
  • Content Count

  • Joined

  • Last visited

  • Days Won


FarmerPotato last won the day on June 30

FarmerPotato had the most liked content!

Community Reputation

2,222 Excellent

About FarmerPotato

  • Rank
  • Birthday 01/01/1971

Profile Information

  • Gender
  • Location
    Austin, TX
  • Interests
    TI-99/4A. FORTH. Verilog.
  • Currently Playing
    Last year: Port Royale 3, Pocket Trains, Minecraft, Master of Orion II, PacMan 256, Katamari Damacy, We Love Katamari, NY Times Crossword
    This year: Katamari Damacy Reroll, Settlers of Catan Universe, Chisholm Trail, NY Times Crossword

Recent Profile Visitors

5,568 profile views
  1. Thanks @TheBF I think my big may be in the TX side specifically use if the RTSON. I’ve got my RTS out wired to the other sides CTS, with hardware flow control on. so having it low is required to enable reception. all the sample code I’ve reviewed, even my own code from 1975, brackets the transmission with SBO RTSON, transmit N chars, SBZ RTSON. I surveyed the code for TE3, TINET, Thierry ‘s titechpages, the 9902 and 990/189 manuals. I figured I want to receive and transmit simultaneously, so leave RTSON on all the time. but nobody does that… problem: I’ve got to unwire RTS out from other end CTS in, if I want to put this code in. I tried last night and it deadlocked…. If that’s the case, I wonder if this is a bug in the 9902 design? It’s unnatural for there to be a extra transmission after reading a char. And I’m positive it transmits after the receive buffer is read, but before any other access to the chip. Doing SBZ RTSON shouldn’t cause any wasted time between characters, since RTS stays on until both the transmit shift and buffer registers are empty. Simple hardware change…
  2. I tried one of the new 9902A . It transmits without any glitches. Source was specspecialties. I still have the weird problem that in the receive function I see a FF go out the TX line, without even loading the transmit register. * RBRL indicates a char is ready STCR *R7,8 read the char SBZ RIENB bit 18, clears RBRL In fact the TX line activates one cycle before the SBZ RIENB. It’s like some goofy half-duplex behavior
  3. I too noticed the 9903s. I’ve not been able to find one but I’m satisfied with 9902s. The 5502 is a bubble memory controller aka TMS9916! https://www.lo-tech.co.uk/downloads/manuals/texus-instruments/TIB0203.pdf the purple ceramic chips 3011? Not sure of the markings. My guess—small RAMs?
  4. @oddemann we learn more of the story every year, this is what happened: The TMS9940 was supposed to be the home computer CPU. It was so awful, buggy, and behind schedule, that it had to be killed. The home computer team was prototyping with a 9900, and that had to be shoved into the home computer. The 9995 was a superior design, and it filled the slot for a 40-pin, 8-bit data bus CPU. It outperformed the 9900. The 98/8 and Geneve 9640 showed speed, plus decent and good software compatibility. The TMS99000s were never used in a consumer product by TI, but Cortex showed what it could do. It combined the improvements of the 9995, an external 16 bit bus, and double the speed. But even a 9900 on a proper 16-bit board is nice and can be built compatible with most software.
  5. I would gladly help you find a use for those chips I think the 3456 is the video chip for the hexbus display?
  6. ROTFL. The contract defines Net Sales as net loss. This was really interesting to see.
  7. LREX/LOAD I’m curious how the Load Interrupt was used on the 990 or TM990. Also known as LOAD, NMI, and related to the use of the 9900 instruction LREX—Load and Restart Execution. *Bootstrap Loader* I see many (all?) 990 had EPROM at FF00 or FC00. The FFFC load interrupt vector (unchangeable in EPROM) branches into code to do some hardware “self-tests”, and then loads the OS from whatever tape or disk. Then I think I guess it called the RESET vector? (BLWP @0) I recall Dave Pitts put a disassembly of a ROM on his website, and that made it into Bitsavers.org. I think this makes sense for a logical separation of hardware initialization, loading the OS, whereas RESET can be a warm start. On the TI-99/4A, the RESET interrupt does initialization and starts the operating system, which we call GPL. THE 4A doesn’t rely on LOAD interrupt. It requires 32K RAM expansion anyway. So we use it for print screen or a debugger or game cheats. Also the 4A doesn’t implement any external instructions —LREX, IDLE, RSET, CLON, CKOF.) *Single Step Hardware Debugger* The 990/189 user manual or course workbook (I forget which) describes how to use LOAD to built a single-step function in hardware. That circuit raises NMI on IAQ, and I think it must be changed (right?) for CPUs that pre-fetch the next instruction, like 9995 and 99105. *Questions* What did the RESET vector do on a 990 or TM990? what kind of initialization did the 990 ROM do, that the RESET vector might assume already done? After bootstrap, how did the system enter the OS? Through the RESET vector (BLWP @0) or something else? Was the LREX external instruction able to activate a hardware LOAD interrupt on any boards/computers? If so, was the RSET external instruction used for something different? 990 users, can you share your insight into these areas? *COLD* In TI FORTH (4A version) the word COLD I think does BLWP @0 ( anything else? I think it locks up from not clearing user interrupts) I understood this as Cold Start. But from the point of view of the TMS9900 with LOAD, isn’t it really a Warm Start? In TI 990 FORTH, what did COLD do? BLWP @FFFC for LOAD? My Ideas I imagine using LOAD for bootstrap of a 99105 system. On power-up, there were would be EPROM at FC00-FFFE (assume Flash EEPROM.) This ROM would bootstrap the executive BIOS, and then perhaps a choice of GPL or GeneveOS. Also, a BLWP @0 or even front panel button would warm reset into GPL or whatever, not reboot the whole computer or reload the OS. (Instead Use the LOAD button for cold start from a lock-up.) With PSEL active (engages the 99610 or memory mapper) the EPROM would disappear, and FC00 would default to paged RAM. This would let user programs have FFFC for their purposes. It could still be configured as a single-step hardware debugger or print screen (Kudos to @Tursi and others who implemented software debounce on LOAD in the 4A.) . The front panel LOAD button would have to do some extra work to bring the EPROM back. I’m not entirely sure that this can be reconciled with front panel LOAD and RESET buttons. I guess there is an answer in the 99000 data book where the flowcharts spell out what interrupts do. Most (all?) interrupts clear PSEL and PRIV status bits (while storing prior values in R15 to be restored by RTWP.) If that’s true of LOAD, then it can’t be used to execute a vector in RAM. And the single step hardware debugger has to be integrated in the EPROM. I guess I want both a front panel LOAD button, and a distinct STEP button. The power up behavior would clear and raise LOAD, instead of RESET. Typical circuit is an RC discharged by the button, then charging up, plus a Schmitt-Trigger buffer LS14 to debounce and make a clean signal. On power-up, the 99105 emits a bus status code of Reset. I decode this (LS138) to generate a backplane RESET signal . This is called IORST in E-BUS. IORST is a more specific name that activates any RESET pins on backplane devices. Does the RSET instruction emit the Bus Status Code for Reset, or just the CRU bits indicating external instruction? I know I could chase down these answers, but I only have a phone right now. And I’m interested in y’all’s perspectives.
  8. There’s a lot of things that don’t make sense to me about E-Bus. I understand the arbitration sequence, but not how a 9900 could use it. CRU reads look like idle states, so nothing to trigger a bus request. 99105 has adequate information in the Bus Status codes. Timing is slow if BUSCLK is 3 MHz. The design guidelines indicate that higher speeds (limited to 10MHz) require a 4 layer backplane. It takes at least two rising edges of BUSCLK before a bus access can begin. That’s two wait states added to every bus access (given 3MHz.) That’s before any waitstates for the memory. it’s a bigger disaster for the 99105 at 6MHz. To meet memory timing at 6MHz, the early read/write signal must get out to the bus, well, early. I imagined there would be a way for 2 equal CPUs to interleave access to the main bus, but I don’t see how that’s possible in an efficient way. More questions than answers. .
  9. I see you want the TMS9650 for Tony Lewis’ math coprocessor card. How many chips did you find? I’ve been curious about this chip since reading the data book at SMU. It gets my imagination going. It could be recreated in an FPGA. which would also be overkill, as the whole math coprocessor could be implemented in FPGA plus a FORTH core too (J1A for example.) My design philosophy is to use real chips, or no bigger FPGA than necessary to replace an old chip. Hard to comply with in this case because the TMS9650 needs 256 bytes = 2K bits of RAM, plus some bytes for registers. that would be many separate chips if done in discrete logic (bunch of buffers or latches, a RAM, one GAL16V8 perhaps.) (Bonus cred: use an original TI 2Kbit static RAM.) I don’t know of a cheap, low end FPGA that has just 2K bits of RAM to replicate the TMS9650. But perhaps the full 256 byte RAM is unneeded? I see harder-to-find Xilinx 95xx 5V parts in people’s 4A designs to date (NanoPEB for one.. Tipi @jedimatt42? Dragon’s Lair? @Tursi) I’ve played with the Lattice MachX02 dev board (my first FPGA) The $5 3.3V MachXO2-640 is small-ish , has 18+5 Kbits of RAM, in a 48 or 100 pin QFN 0.5 mm pitch. But in the semi shortage, it’s unobtainable for a year out. I still think about the 3.3V ICE40HX1K as a “lower end” FPGA part for $5, and still that has 64Kbit of RAM onboard. It uses OTP or external Flash (any cheap 25x series) Overkill. Whereas the E-Bus arbiter 74LS2001 could be done in a GAL16V8 ($1 new from Mouser). just it can’t do the exact 74LS2001 pin out with its stupid power pin placement (sorry, Cortex owners) but same package size. Background I’ve learned about 3 vintage 9900 parts for multiprocessing: The 74LS2001 does bus arbitration between multiple COUs or DMA memory. (Thanks @Ksarul for posting E-Bus.) The 9650 arbitrates internal access to its RAM among two ports, through the READY line, but assumes separate buses. For two equal processors on one bus, the 9650 calls for a bus arbiter like the 74LS2001. For a coprocessor, (math, peripherals etc) there is no need for a shared bus. Finally , the 99105 has MPI lock out, to implement semaphores in test-and-set style. In a 99105 multiprocessor arrangement, you still need a bus arbitrator to keep the bus during MPI lock, during which the source operand is read, bus sits idle, then operand written to. ABS behaves like this on the 9900 to implement test-and-set. In the 99105, ABS does assert MPI lock, alongside instructions Test and Set, Test and Clear Bit. I haven’t familiarized myself with the TMS9911 DMA controller, which seems to be available (though I’m skeptical.)
  10. There is a original TM990 power supply I can pick up locally. I just don’t know what I would do with it. Bring it to a future fest to trade? Texas Instruments TM990/518A Low Voltage Power Supply For TM990 Microcomputers. I am guessing that I might find legacy 990 things given that DSEG was based in Austin TX. Just not sure what I would do with bits of TM990 and that AT clone TI 955 monster. I’m currently going for TI Omni printers—I absolutely loved the 132-column Omni 800 I got as a junker in the 80s. It ran solidly for a long time. . a while ago, I passed one up on Craigslist that was retired from duty after printing wide forms for 20 years. Free. Still wish I’d gone to get it. So I’m getting this 80-column TI Omni 800 model 855 which was supposed to combine daisy wheel AND dot matrix. excited about reprinting my game manual! (Though stuff looked good laser-printed, using retro Elite mono space font with Apple Pages. But that feels like cheating.)
  11. I stumbled on the TI 955 over-there today. At first I was intrigued, until I began to figure out the only big chips visible were EGA and some BIOS EPROM. The hint about 8 or 12 MHz startup speed reminded me of the clone era. But it is local pickup for me... The photos are also at https://wiki.preterhuman.net/Texas_Instruments_955_Workstation I also stumbled on the ASC PAD manual, same seller as a $100 990 Pascal manual. I do not know if the PAD manual is in DeGolyer but I will be sure to check if/when I go there again. I only read the one book about "History of TI's early computers" covering the ASC.
  12. @Jimhearne i think B is possible, factory reject, and that these chips have been fake labeled and sitting in a warehouse ever since 1988 or so. Several were defective in the same way. They don’t look used and the pins were perfect and splayed out.
  13. On the call yesterday: Who was the person looking for a 99/4? I'm actively looking, and will share finds.
  • Create New...