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FarmerPotato

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FarmerPotato last won the day on April 9 2023

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About FarmerPotato

  • Birthday 01/01/1971

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    TI-99/4A. FORTH. Verilog.
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    Last year: Port Royale 3, Pocket Trains, Minecraft, Master of Orion II, PacMan 256, Katamari Damacy, We Love Katamari, NY Times Crossword
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  1. Thank you Gary, the blog gives me a much clearer idea how teletext came together. Colin Hinson's blog describes using (and inventing!) the particular assortment of Teletext and 9995 boards that Stuart is listing... I've wanted to know more about the Bedford office. The blog writing is vivid. TIdings, Bedford's site newsletter, is listed for 1979-1972 in the Texas Instruments Records at DeGolyer.
  2. Curious about the several Teletext boards shown. They show the TMS3556, a versatile VDP ideal for showing text in multiple colors. (Used in ExelVision) I found a mention of Teletext chip sets from French companies RTC (Phillips), EFCIS, and Texas Instruments France. Prepared for the Antiope teletext system. Teletext was/is digital data piggybacked onto the analog TV signal.
  3. Some bits about the /1481 and the /306 Speech Board in Electronics. I hunted through the 1980 issues. Also found a block diagram for the 1481 -Osborne book probably taking after the Microsystems Handbook. Another item describes the Analog Devices ATE (automated test equipment) for linear ICs, as a TM990 floppy based system. Could that 16-slot rack be related? Bunch of Analog A/D boards there. Thread: "Working with a TM990/100 or 101M CPU, the new TM990/306 module can verbalize 179 words, including 0 to 12 and A to Z." [Electronics, Mar 27, 1980, p. 84] and [Electronics, Apr 10, 1980, p.84] [Ads for TM990/306 Speech Module for $1280]
  4. Question about TM990/307 IO ports: Since XDS/22 once had a 307, I need to know the 307's port addresses. (my XDS in 1989 hasnt got a real 307, maybe a hybrid derivative). My guess is: CRU 0000 port 1 9902 0040 port 2 9902 0080 port 3 9903 (yep 03) That is the order in the 990/5 machine. XDS labeled port #3 is the only one fitted in mine. So, it's the user terminal, the host. Host may be CRU 0000 port #1 internally but labeled port #3 externally. The disassembled PRTCHR XOP branches depending on port. Some SBO/SBZ are definitely not for 9902. Guess 9903. It seems to honor outgoing XON/XOFF only on one port. If sending a Ctrl-S (XOFF) it truly zeroes RTSON. Transmitter off. Maybe this is for huge file upload from host. Maybe printing...
  5. Wait, what? The MVP is 320C80? Or the other way round? Another is the TVP4010 and up. These were in late 90s gaming 3D accelerator graphics cards. GLint accelerator. Seems Texas Instruments did make inroads in mainstream graphics cards.
  6. Very! The 990/12 had 64 bit wide microcode for the 481s. Soldered in. I think I see the 1481 with ten sockets? So 80-bit wide. Plus that daughter card... The 1481 is a 9900 built from TTL. Not necessarily the TMS9900 but definitely a family member. With the 1481 microcode ROMs, you'd have a crucial tool to make a 9900 simulator at the silicon level. @mizapf Plenty of difficulties, but maybe Texas Instruments made it fairly close to a documented architecture. I've made notes on what I found so far.
  7. OMG that is a bunch of SE9996 chips, and one marked TMX9996! Im interested in chips--a SBP 9900 and 9989 are exciting. Ceramic 9900 because it's beautiful. And some 9996. I was pondering whether to sacrifice one to get decapped. Check if an XDS has had its SE9996 pulled. If either XDS is the 9995 emulator, I'm very interested. (99105 would be priceless.) (You should bring one online!) Any system really besides the 34010 I've got. Yeah, they are heavy. About 40 lbs. I hesitate to ask for just a set of cards sent overseas, but I think you could repurpose the chassis to TM990. I'm interested in any XDS manuals, but I feel first that they should stay with the matching XDS box. The TM990/1481 is an incredible gem. At the same time I see this board in the 1982 price list, the 74S481 bit-slice chips that it uses (4 of) were not for sale. The Microprocessor Systems book shows it NRD. I would dearly like to study that 1481, and dump the microcode ROMs. It's going to be close kin to the 990/12. That said, I've got a 990/12 to study, and I bet someone else would enjoy it.
  8. It's just too many ideas. I've been interested in the 340 since I came across its Font Library booklet. Maybe by 2030 I could add it to Geneve 2020... Incidentally, I was looking at the MVP a week ago. Pretty sure it is the upcoming chip Karl Guttag described in the 1992 Delphi transcript. I read the Hot Chips presentation. It is way, way overkill for retro. https://old.hotchips.org/wp-content/uploads/hc_archives/hc05/3_Tue/HC05.S5/HC05.5.2-Guttag-TI-MVP.pdf
  9. The bits for the 9901 at 0000. keyboard, joystick, interrupts 1 and 2. Setting the 9901 to Timer mode. RS232 Bits, by usual name for 9902, at 1340/1380. Parallel at 1300. This is tricky but perhaps someone can ( @TheBF!) can highlight the important ones. Format for tables of CRU: By base and bit offset ( the address would go up by 2s where offset goes by 1s) Base 1340 ie LI R12,>1340 Bit offset N for SBO N SBZ N Base 1340 Addr Offset 1340. 0 1342. 1 1344. 2 etc
  10. I've traced out most of the 9996 pin connections. A hypothesis --the die is rotated vs the 9995-- helped guess and prove MEMEN. I've used this to narrow down where to look for other pins, but several like RESET, NMI, HOLD, READY are probably all wired to VCC without even a resistor. Where the 9995 has pins INT1, INT4, I find the full set of 9900 signals. The code uses interrupt levels 1, 2, and 5. 7-15 immediately RTWP. The others go to RESET. SE9996 CPU at U60 1 MEMEN* 2 NMI or RESET? 3 same 4 5 ?VCC, or READY? 6 7 A15 (MSB. TI A0) 8 A14 9 A13 10 A12 11 A11 12 A10 13 A9 14 A8 15 A7 16 A6 17 A5 18 A4 19 GND 20 A3 21 A2 22 A1 (LSB. TI A14) 23 CRUOUT (maybe A15 if used) 24 XTAL 25 XTAL 26 unknown. CLKOUT? 27 28 D0 (LSB. TI D15) 29 D1 30 D2 31 D3 32 D4 -- 33 D5 34 D6 35 D7 36 D8 37 D9 38 D10 39 D11 40 D12 41 D13 42 D14 43 D15 (MSB. TI D0) 44 GND or ? 45 GND or ? 46 IC3 (from 9901) 47 IC2 48 IC1 49 IC0 50 INTREQ* (from 9901) 51 52 53 CRUCLK 54 55 56 to PAL 57 58 to PAL 59 VCC or ? 60 61 62 RD* 63 VCC or guess HOLD 64 WE* The PAL at U71 has: 1 ? 2 ? 3 MEMEN* 4 RD* 5 CPU 56 6 CPU 58 7 CRUCLK 8 CRUOUT/A0 9 CPU A15 10 GND -- 11 CPU A14 12 Enable U62,63 13 14 EPROM A13 15 16 Enable RAM U69 17 Enable RAM U65 18 19 20 VCC The story here is that the PAL is able to translate the top 2 address bits from the CPU. It also produces two signals to enable the RAM upper/lower bits. There are two 27C512 EPROMs for total 128K ROM. The lower 13 address bits A12:0 are driven by CPU A13:1, so the page size is 8Kx16. (4 pages fill a 64Kx8 address space.) The next EPROM bit A13 is driven by PAL U71-14. The A14 bit goes to a jumper. There's A15 yet to be traced. The jumper goes between either VCC or something else (not GND.) So the EPROM may hold two jumper-selected variations of the software. There are two 6264 RAM making 8Kx16. The RAM have separate enable signals out of the PAL. I speculate that CPU 56 and 58 may indicate upper or lower byte access. I know from disassembly: 0000-3FFE resident ROM 4000-7FFE mostly data 8000- ? probably memory-mapped devices like the two TMS9650s (256x16 memory) C000-Exxx must be RAM. There are several tables of address pointers that support this. I traced out two '138s decoding CRU access using A11:6. A15-13 (MSB) are 000 for CRU, else the external instruction code A12 - have not traced A11:6 are decoded in the 138s along with MEMEN A5:1 go to CRU devices such as 9901 A0 - not part of CRU address, it's CRUOUT data. I have not figured out CRUIN - doesn't seem to go directly from 9901 to the CPU.
  11. Wow! So much to look at! #1 The last 8085 board has a NEC 765 floppy controller and two 34-pin connectors look like 5.25" floppy. Could be a 50-pin cable for 8" floppy. #2 The 9995 emulator has some features I recognize from my XDS/22 boards. The "pod" on a 2x2x40 cable that would go to a 9995 socket. (looks like extra GND in between all 40 wires) Row of fast AM9128 RAMs (70ns) for trace data Row of even faster cache RAM (45ns) next to it Weird though: if this is a single board emulator/trace module, how do you use/connect to it? With all the 1981 chips (but 1985 CPUs?) it's closer to the AMPL generation. In my XDS/22 the BTT (breakpoint-trace-timing) module has the 2x2x40 connector. I dunno what for, since it's a separate card from the emulator (emulator provides the external CPU pod.) Clearly some family heritage between these boards.
  12. Did not see the card cage! I saw the prototyping card last week though. Nice! Unrelated, radiodad has this connector sample pack! It's all the common PC ports circa 1999. I would have appreciated this set, instead of shopping for a few of each from China. Then again, peconnectors.com (Phoenix) is also an awesome source. Getting the T bus connectors are another story (I bought four, 2x50 solder tail, on eBay). https://www.ebay.com/itm/256425520074
  13. There's a thread about this somewhere here. It has the display device protocol in it--for the one that Texas Instruments had working. I found a cheap (<$20) VFD display. Futaba brand, I think. 40x4. Chars are 5x7 dots. Usual ASCII characters and 7 ? Slots for user-defined chars. Interface by I2C or SPI (just send it 8 bits for a char.) Thought that would be a nice upgrade. *VFD=Vacuum Fluorescent Display, what we had on VCRs before blue LEDs. (hate blue LEDs.) Speak n Spell type.
  14. Oh, it's both horizontal and vertical travel. Horizon isn't fixed. Would it have to be a contiguous row? Address calculation gets messier-- MOV R3,R0 Row SLA R0,5 MPY by 32 A R3,R0 A R3,R0 But I guess you would be refreshing the whole table in one go, so VDPWA is set once. For scrolling, I made TL2 into four screens, so the refresh portion is always off-screen. TL1 scrolls half the speed so I allocated just 64x30 & refresh off screen.
  15. (5 years ago, yikes) I tried a BML to mask out the bottom 3-4 rows of the screen. TL1 and TL2 were scrolling (different speeds) for a parallax effect. I wanted a fixed status display at the bottom. (The old "scrolling window" feature was gone.) BML would cover ties 21-24. Row 21 would be solid BML to hide partial tiles. Tiles to be erased after scrolling 8 pixels. I would draw status into BML for rows 22-24. With a 256x32 bitmap, 2 bits per pixel, I got a very confusing result. (Hardware F18A, recent firmware.) Probably my error, but to clarify-- Is there a way for the BML to mask both TL1 and TL2? Sprites aren't an issue.
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