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FarmerPotato

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About FarmerPotato

  • Rank
    Stargunner
  • Birthday 01/01/1971

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  • Gender
    Male
  • Location
    Austin, TX
  • Interests
    TI-99/4A. FORTH. Verilog.
  • Currently Playing
    Last year: Port Royale 3, Pocket Trains, Minecraft, Master of Orion II, PacMan 256, Katamari Damacy, We Love Katamari, NY Times Crossword
    This year: Katamari Damacy Reroll, Settlers of Catan Universe, Chisholm Trail, NY Times Crossword

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  1. Goldangit. my first attempt to build a 9995 Computer, I pulled the CPU from the 99/8. I used F000 as the workspace. I thought I fried the chip cuz not even the simplest code worked. Later I got it back in the 99/8 and it was ok... I took a chip out of an SBC built by Mike Read (bar code reader) and started to get somewhere.
  2. Since 1989, when I left for college, (Compuserve TI forum sysop) Jerry Coffey has the 99/8 I got, and a disk drive that I don't recall ever working. I did write some basic programs for random walk fractals, since it has bitmap mode commands. But not much else, because no working storage. Jerry also bought a end-of-life Myarc WDS1 that served me a lot from 1985-1988. (the drive developed a bad starter relay, that was all. ) Alas, nobody bought the PDP-11/10, and my parents made it go to the scrapyard. I wish I could redo time and keep this stuff. The 99/2 was too small to worry about, and lived in a box of books, for years. Until I rediscovered it. Craziest thing all at once: in 85, with no modem except the one for the CC-40, I used a 4 line CC-40 Basic program to bridge the modem to the hexbus rs232 to the 4A. PC Pursuit had free weekends. I was able to download the c99 package by xmodem over that connection, to the 4A, and save it on the WDS1.
  3. Following along with great interest. I thought I'd share some of the SN76489 music I've bookmarked: This is some really good PSG music (SN76489) https://tomy.bandcamp.com/album/psg-series-1 from https://www.smspower.org/forums/14380-TomysPSGSeriesSN76489Music Especially "Assembled in 1987" Good attacks on Cotton Candy Glazed Eyes is not too monotonous On Tomy's PSG 5, The Outsider has an interesting low-frequency beat. It sounds like sequential periodic and white noises, with attack using white noise, then periodic noise in the decay. Sometimes it's periodic noises with a jump in frequency. https://tomy.bandcamp.com/track/the-outsider-2 Tomy records from a Sega Master System.
  4. This is amazing, Rasmus! I was stuck trying to figure out what kind of maze would help my Katamari demo be a game. If I were going to back to that, instead of just scrolling 2d bitmap, I would like to do something like this. There would be a lot of sprites for the things you run over (the object of the game is for Munch Man to roll over all the sprites and get bigger.) Will you be sharing the source when you are done?
  5. I noticed the total posts in Development. It's 65336. My optical cortex is trained from childhood to find 65536, and other powers of two, on the screen. (I used to be afraid of the number 32767 because it meant TI BASIC was about to crash. Or a RESEQUENCE had found a GOTO with a non-existent line number. Harmless.) Anyhow, AtariAge will probably not roll over the post count to 0. It's not running on a 6502. But the person to write post >10000 gets a special prize. No cheating!
  6. It is fascinating. My only idea was that a list of tokens referred to dictionary addresses in VDP. Like your idea. I look forward to your working out how to use the tiny memory Surely there has been a teeny tiny FORTH in all its history? Just kidding, you are under no obligation to solve such an interesting exercise!
  7. Online order replaces what we put into the spreadsheet? I placed my order online. Also I was not sure what this meant: >I am opening up the PRE-ORDER effective immediately. The preorder will last through June 25, 2020. No new pre-orders will be offered for this round. Does 'No new pre-orders' mean nobody but those who pre-pre-ordered on the spreadsheet, or can anyone join, thru Jun 25?
  8. I'm with you on that. I just had too many 3D books, most of them picked up 50% off at The Strand (where all the review copies went to find new homes). Maybe I didn't judge the quality of that one correctly. Don't worry, I still have an enormous number of books.
  9. Yeah, 612 would be fine. I would not use the latch. (or is it the 612) I think that's 4.40 each chip. Four of the DIP40 would take up a lot of space. The F package would be nicer. Actually Rochester has them new, min qty 51 at $5 https://www.rocelec.com/search?q=74ls612 But... it's likely I would move up to reproducing it with, at least, an ATF1504 at $4. But with the lower Atmel parts, I found the WinCUPL tool compile/run test vectors to be a miserable process. Still, these are not too overpowered.
  10. Hey, I had that book too! After 2001, I kept mostly OpenGL books.
  11. Since there was no status update in May: Status June 10 The CPU board is arriving from SEEED next Monday. Then it will be time to assemble and debug it. I will test it with a NOP (>1000) hard wired, called "free running." The BIOS memory card is routed, but not sent, pending some QA. This will hold the initial software in EPROMs and provide some RAM. The CRU/Serial 9901/9902 card must be started over. It was once integrated on the CPU card. The 8-slot backplane is here. Everything will be based on 160x100mm Eurocard standard, Cards can be 100x100mm if you like. In fact, the backplane is an ECB-Kontron compatible backplane! As a result, I anticipate the ECB Disk IO V3 off-the-shelf will provide DSDD floppy and IDE access, but require re-writing drivers (The supplied driver is in Z80.) Some parts of the 8-slot enclosure is here. It is going to be super classy, but cost $150 including backplane. Optionally, you can put the naked backplane into a PC tower. A 12-slot backplane and enclosure is possible, or a 4-slot (I have to combine some cards to make that viable). I am going to give a PCB order to Aisler - they will make one for about $40 shipped to me, in US or Germany, not much more than $30 with shipping from China like SEEED Studio. Or $80 for a 10x10cm from OSHPark, yikes. Features implemented: The 16-bit bus and 8-bit peripheral bus (VDP, sound, Pbox etc) are unified on one backplane. Access to 8-bit cards will be direct when memory-mapped ports are enabled, and always possible through CRU byte-or-word-parallel (two cycles vs one for memory mapped). The CPU card drives 15-bit address and 16-bit data lines and all other CPU outputs to the bus. It adds several useful signals like IO parallel and serial, and generates some ECB specific signals for compatibility with Z80 cards. The CPU card supports external Macrostore and attached processor interface (think floating point coprocessor.) It supports external RESET and NMI buttons. The BIOS card decodes Macrostore access (integrated into the Page 0 EPROM space, not a separate page.) It supports supervisor and user memory spaces. It supports one 16K ROM page 0 and one 16K RAM page 0 always present in supervisor mode, and bank switches additional 16K pages of ROM and RAM (currently 8 pages of ROM, 16 pages of RAM.) It also has nice LEDs. Not implemented Plans for the DRAM card amd memory-mapping are wired into the CPU and BIOS cards.. the DRAM card will have the memory-mapper, making a 32MB user space. VDP is still sitting on my desk. It generates 15kHz different RGB screen colors.. But I have not got it to sync with the Acer monitor yet. It will require a revision or a bus adaptor to use. FPGA is back to the drawing board. However, it's becoming less necessary, as more functions are implemented in real chips. The bring-up system will run software without it. However, the SD card filesystem is in my FPGA so... I have found a ready-made ECB Disk IO V3 floppy and IDE controller. It is uPD765 compatible (IBM 360K). It's not too different from Thierry's IDE, but drivers will have to be written.
  12. If I could get these for $2 a chip, I might want to put 4 of them in Geneve2020. Otherwise I'm using a $8 CPLD to replace them. Using vintage chips is a goal. Why four? Well, I'll post that over on my thread, not to hijack this one.
  13. If I could get LS610 memory mappers for $2 a chip, I might want to put 4 of them in Geneve2020. Using vintage chips is a goal. Otherwise I'm using a $8 CPLD to replace them. Why four? For starters, the Geneve with 9995 has an 8-bit bus. Reading a word from page registers at >F100 means 2 reads of separate 8-bit registers at >F100,>F101. Ditto for writing. MDOS assumes fast context switching by doing four MOV to save/restore the registers two at a time. The 9900 and 99105 read/write 16 bits. Without nasty multiplexing, wait state generating circuits, there's no way to read and write 2 registers in that MOV instruction. Unless you have TWO LS610 chips! Then one holds the odd page number, the other holds the even page number, both are attached to one half of the 16 bit bus. Hooray. This is assuming you want only 8 8K pages. Using just 8 bits of the registers gives you 256 * 8K = 2MB of address reach. Problem solved by 2 chips, right? Now I'm going to assume a SECOND row of LS610 to extend the registers! The LS610 registers are actually 12 bits. Each register occupies 8 bits in one LS610, wasting 4 bits. I want all those bits! But in the above scheme, every write access would destroy the upper 4 bits (unless you could somehow loop them around. YUCK. You can't count on read-before-write to capture them.) The SECOND pair of LS610 holds more bits! When read/write at >F100, that chip stays silent, retaining its value. When accessed at a different, word address, the read/write data is multiplexed in a different way, to load one 16-bit even register or one 16-bit odd register. Picture: 16- bit stitched-up registers spread across four LS610s (wasting 4 bits per chip, and using only 1/4 of the registers in an 8K page scheme) E1 E2 O1 O2 E2 E1 O2 O1 MOV @F100,R1 * R1 is from E1,O1 MOV @NEWPORT,R1 MOV @NEWPORT+2,R2 * R1 is from E1,E2 * R2 is from O1,O2 The upper half being a "base" address for the MDOS instance, that does not change. Four of those bits gives a reach of 32MB, which ought to be inexhaustible. I use the other bits for status flags--currently I want 3 status bits-- namely read-only memory (ROM), some ports are memory-mapped (SPAMM), and p-box pass thru page (PBPTHP). But there would still be 1 bit left, and 4 wasted, in the upper register! (I have not thought of a way to get 4K pages in this scheme... wasting half the registers.. actually 75%, so 2K pages could be wished for. But hopeless.) So that's the scheme using four LS610s. It's pretty crazy! I will probably just use the CPLD to implement 16 16-bit registers. (I also looked at a 4x4 array of LS670 4x4 register files to do that. Blearg. Might as well use 4 8K SRAMs. Gross.) I'd like to use real chips, but not if breaks compatibility or gets stupid crazy. Doing it in CPLD allows other magic things to happen, like fast map switching, but I'm not sure if I want to be a purist or not about that. Why 32MB of address reach? You can get new 1MB,4MB, or 16MB SIMMs in a pair. 2MB for starters, one MDOS. 8MB enables switching between two or more... or implementing a separate RAMDisk or giving GPL SAMS memory that allocates outside the MDOS space. (Howver , the price difference is $10 for 2MB, $30 for 32MB brand new, or find them used.)
  14. The Sandbox is mind-blowing. Imagine if people had known how to exploit this back in the day - commerical "BASIC" cassette programs that get around the bottlenecks in TI BASIC! 99'er magazine reviewers would be stumped at how a program got that performance! Imagine a FORTH environment that targets the Sandbox loader. FORTH might be a good way to leverage the tiny page size! A word would have to be limited in its compiled size to very tiny. The stacks would be similarly limited. Perhaps static analysis could determine in advance what the required depths would be. (or at least run-time tests.) In the end, a FORTH program that executes from a bare console in BASIC, with mind boggling performance nearly as fast as assembly, certainly faster than GPL or BASIC!
  15. Hello! I've been looking at ways to mount backplane/cards in a common Hammond enclosure ($50-$90) and mATX form factor. I know you and others here want a bigger box (10-16 cards) but I am thinking of a smaller one with 3 cards (plus built-in flex) and a half-height bay. Another approach I pondered is a 4U server rack. These are expensive though. I have a hunch that a 50-pin SCSI cable would be a better way to connect a flex card to a console boot. Users could pick their own length (within limits). You said backwards compatibility plus a miniature size? How would that work? I don't think re-buying all the cards in smaller sizes is in the cards (sorry).. people DO want to use their existing storage controllers, and nobody has made a new floppy controller, plus chips are getting rare. Thierry's IDE as you can see from Shift838's build would be tough to make any smaller... though it has been done for retrobrewcomputers (formerly N8VM). I'm looking at their DiskIO V3 IDE/floppy card, similar TTL implementation to Thierry's IDE. Its size is 160x100 EuroCard single. Compared to the a P-Box card at 195*150mm, that's about half the PCB area. It uses a SMC 9266 FDC.
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