FarmerPotato

Second that. I built ought on a wire wrap perf board once I had the Geneve2020 CPU module ready to plug in. Memory, 9901, 9902 and sundry went in wire wrap first. Im tempted to go back, or a combination of PCB with next steps in WW. So much trouble soldering my latest boards. Along the way, I learned some history of wire wrap. It is a superior technology! Connections, physically, are superior. Breadboard doesn't compare. . The standard Radio Shack WW hand tool is still reliable. (1980s). Got the parts to a Jonard electric tool, but still the hand tool is second nature.

I bought from him a keyboard compatible with my TI-928 terminal. It was in amazing shape and so an amazing value.

I researched this recently. I was going to start a thread of "other Texas Instruments instruments". From memory: It connects by DB25 to a PC where you run WINSDS.EXE. That software sends your audio samples to the box which has a TMS320C6xxx in it. (Or some flavor of the 320 DSP, I forget.) Alternately, it can synthesize speech. The DSP extracts MELP code parameters, not LPC-10. For playback on one of the late speech processors. So, even if you had the software, it would be of no use for Home Computer speech which is LPC-10. I found two datasheets that describe the SDS-6000. They do have the guidelines for getting good recordings. Pretty cool that, ultimately, Texas Instruments distilled the speech analysis workstation to a little box. Compare @Stuart's big SDS workstation. I found one mention of a little box like the SDS-6000 that still did LPC-10. Maybe SDS-5000?

Many, many thanks, Colin! This is the most exciting databook I could have read. I have been reverse engineering my XDS/22, TMS34010 emulator. Like the first XDS/22 for TMS7000, it has an SE9996 just to run the XMPL software (or whatever they called it by 1988). At first it was a greatly satisfying puzzle, to trace or test out continuity for the 9996 pins. I deduced the set of pins that match the 9995. Made some guesses like 'pin 56 to PAL could be the necessary byte/word signal'. Your databook confirms those guesses, but fills in all the mysteries! FREEZE, MAP, MID, 9995se/9990-- I could never have figured those. (9995se/9990* is grounded!) The EPROM is two 64K byte images selected by a jumper. There is 16K of RAM. The PAL generates chip selects for EPROMs or RAMs. It re-maps the top address bits. The code proves that C000 must be 16K RAM, and 8000-83FE is memory mapped devices. But I didn't know how it gets to C000 in EPROM. The 9996 databook pin 58 is the inverted ST8, MAP0/MAP1. Similar to 99105 ST8 Map Select. That goes to the PAL too. I looked for code that does LST (Load Status) and found subroutines that set/clear/restore ST8. So that's the clue to unravel how the full 64K is accessed. Thanks again!

Nice. That's a TM990/101MB, the last version of the 101. It's a great board to see how Texas Instruments would take advantage of all the features of the 9900. For instance, the single-step capability and DMA memory access grant. $113 was a great price! (though you still need to have a backplane, or at least power hooked up.) I have a 101MA and 102, so I'm good for now.

Here is the correct link, where the Specification was posted.

I'll bring two 4A with P-Box and speech. One is Geneve 9640. Also a console with F18A and TIPI/32K. Anyone is welcome to demo on those. Particularly, F18A VGA out for projector. Other exhibits: Collection of Texas Instruments talking toys. Artifacts from Texas Instruments over the decades.

For BASIC, I think you would want to use familiar units like seconds. I first learned what a millisecond was from Beginner's BASIC. "Oh yeah, 0.25 seconds, 250 ms." Thinking in "ticks"of 1/50th would be more nerdy. TIBASIC insulated you from machine implementation, unlike others with PEEKs and POKEs and OMG AppleSoft shape tables. (Packed byte of 3 "turtle" commands.) Shame there was no calibration for NTSC/PAL. At least the frequencies are both 3.579 MHz right?

Edit: I put the link for the C.B. Wilson papers thread into my above post. That's where to find the full 255 page Basic specification.

Wow. Interesting bug testing, @OLD CS1 Here is "File Control Statements" from Specification for Texas Instruments Standard Basic, pp. 55-59. That is the "Green Book" from the C.B. Wilson documents (see documentation thread.) It's a really interesting book. You can find the definitions for PERMANENT / TEMPORARY and KEYED. And the SCRATCH command. It also shows CLOSE #1:DELETE. From Chapter 1, I infer that our BASICs were of the EN subsets. EN = Education Nucleus with supersets E1, R2 IN = Industrial Nucleus. No string variables! BN = Business Nucleus. Keyed-Indexed files are required in BN2. TI-BASIC File Specification.pdf Originally posted in this thread:

I have wondered if anyone still makes extra wide space bars.

I didn't notice on my own, but Erg titles it "EIA Colors" so there you go.

In the old days, a wave soldering manual called for chips to face their prow into the wave, rather than get hit broadside. Arrr.

Another interesting offshoot was Lilith (1976). Niklaus Wirth was at Xeroc PARC in 1976 and used the Alto. On returning to ETH Zurich, he had a small team create a "desktop workstation" by 1980. It's really interesting reading, how Wirth re-created the Alto concepts in the Lilith workstation, starting with a very large bitmap display. This article claimed about 310 in use.

I last got wires from Pololu They only have 7.5 cm female to female But other kinds are in sizes down to 5 cm

Originally documented in Shugart manuals, for instance SA-850 drive. The allocation bitmap rules in 99/4 Disk Interface are the same as you'd find in other 990 operating systems. Under Floppy Disk Physical Format, in TX990 and DX10 Systems Programmer Guides. Except that the allocation map was spread over many sectors of track 0, supporting 1.2 MB floppies. Weirdly, AU size could be 1 sector or a multiple of three.

I browsed slide switches at TEDSS.com: page 5 shows an ERG 10-DIP for $10. Website says that they "cater to hobbyists" and "hard to find parts". For this pricing, there is a minimum $20 per line item (so two switches) and $40 minimum order. I could see using a color 2-switch in place of 2 jumpers. For instance BlackIce has a DFU mode jumper next to a serial port enable jumper--not labeled.

Thanks @acadiel . So it's an Erg. Seems they have the category to themselves. And a minimum of $3 per switch is pricey.

Noticed them on Stuart's photo collection!

I first saw the 99/4 in about December 1980. It was an Open House event for families at the Texas Instruments plant in Lubbock TX. Then, the hottest TI product was the Digital Watch with calculator built-in. Coming in second: must have been the helium balloons. Next to the digital watches was a 99/4 (no A) display and a crowd of people. They were waiting to play 'Pot Shot' from the Video Games I module. This was the store display, with modules on retractable steel cables. We got watches for Christmas. I was in 4th grade. My dad brought home a 99/4 in March 1981, from the Texas Instruments employee store. We used our cassette deck for everything. For software, we had 'Oldies but Goodies 2' and 1 module, A-maze-ing. Our dad said 'now learn to make your own software.' So we did. I think we got Hunt the Wumpus and MunchMan in 1982. I didn't see a 4A until Sep 1982, when Texas Instruments loaned 2 systems to our Boy Scout troop. (Both of the Scoutmasters were from Texas Instruments.) 4As with the sidecars for disk and 32K. Each Scout got one Inmac floppy disk. The conditions were: we all had to earn the Computers merit badge and put on a big demo at Jamboree. We kept a 4A at home until Black Friday... when Texas Instruments said "no need to return them". By then, I had spent hundreds of hours programming or typing in programs. 4A was my only computer thru 1988, when I worked all summer to buy a Geneve 9640. Used that until 1992! Still have a place in my heart for those sidecars. The 4A with the loan sticker turned up in the basement yesterday.

eBay's automatic "Inspired by your recent views": What I actually viewed: Texas Instruments Color Graphics Board RARE What it said I should look at: Cray X-MP Memory Board The Color Graphics Controller Board works with TIPC or IBM PC. It is based on a TMS34061 display controller with 256KB of VRAM. (4 banks of 8 TMS4161 64Kbit dual-port). The output is 1024 x 512 display in 4-bit color. The DE-9 port is for an EGA monitor - digital output in 8 colors. A 2nd version of this board would have a TMS34070 palette chip, providing analog output with 16 colors per row (18-bits per color). I thought of it as an evaluation board. Wonder if any TIPC software drove it. The Cray X-MP Memory Board works with... a Cray X-MP. See those QUAD INLINE PIN chips? Those are MECL-to-TTL translators, to isolate noisy TTL circuits. MC10125 type. MECL is a differential signal with + and - traces (like USB D+ D-). RAM is MCM6287L-35. Fast 35ns access time, 64Kbit each. Total 256K x 9 (parity).

I want to start a thread where we can help each other find obscure parts. It can be a fun game, maybe you even need the part for a project. I will get it rolling: Who made these colorful slide switches, and where can you get them now? (IC included for scale.) Seen on Madge Networks 1987 Token-Ring network card (ISA). Made in the U.K.

TIGraph 100 https://www.ebay.com/itm/143208585595 My hunch is this was made in the 1960s to print manufacturing line data. I guess it counted electrical pulses from the back terminals. In 1961, TI needed real-time charts of how many transistors were falling automatic testing. The Geophysical and Instrumentation Division invented countless machines to automate the production line. (Mike Bunyard got his start there.) See Ed Millis' book: TI, the Transistor, and Me: My Dis-integrated Journey Through Texas Instruments. (It has very funny stories too.)

"to the designers distinct advantage" made sense to me--it was a trade-off. But what did it really mean? According to a Texas Instruments patent disclosure, the 9900 instruction set is decoded by the number of leading zeroes. This number selects the "entry point" to the CPU's control ROM (microcode). For each "entry point", instructions share a common operand decoding. None or 1 is Format I 2 zeroes is Format III,IV,XOP 3 zeroes is Format II etc The "BYTE" bit isn't up front in the instruction. So whether it's 0 or 1, it can't affect the entry point. MOV has the same number of zeroes as A (add) and ADD definitely needs the destination to be read. As a result, all Format I instructions fetch the destination operand, even MOV which doesn't need it. 9995 This CPU doesn't need to fetch or store a whole word if the instruction is a BYTE type. Special case: does MOVB avoid read-before-write. (I think it does?) 99000 The 99000 cpus eliminated read-before-write as a special case for MOV. Register to register MOV takes just 3 cycles, where MOVB still takes 4. (MOV: WR read, AUMS, WR write.) TL;DR Much more than just read-before-write. We're going to decode the 9900 instructions at the bit level. You'll see the leading zeros concept throughout. Format I instructions, A or MOV for example, begin with one or no zero. Format I have general destination and source operands. Two leading zeroes means Format III: one destination register, one general source operand. Format I and III examples MOV 1100 Td dddd Ts ssss MPY (format III) 0011 10 dddd Ts ssss where Ts,Td are: 00 register, RX 01 register indirect , *Rx 10 symbolic @Y(R0) or indexed @Y(Rx) 11 register indirect auto increment, *Rx+ dddd and ssss are register numbers. Some longer tables sorted by leftmost bits, counting down. Format I. One or no leading zero. Two general operands. Opcode is 3 bit ALU operation code, one bit "BYTE" flag. Then 6 bits DST, 6 bits SRC. (Total 16 bits) Opcodes: 1111 SOCB 1110 SOC (set ones) 1101 MOVB 1100 MOV (move) 1011 AB (add byte) 1010 A (add) 1001 CB 1000 C (compare) 0111 SB 0110 S (subtract) 0101 SZCB 0100 SZC (set zeroes) Formats III, IV, XOP have 2 leading zeroes. 0011 xx MPY, DIV, LDCR, STCR 0010 xx XOP, XOR, CZC, COC These are 8 similar opcodes made using 6 bits. 2 zeroes, a 1, then 3 more bits. (2^3 = 8.) Leaving 10 bits for operands. Opcodes have started to nibble at operand fields, eating Td first. Decoding: 001x xxdd ddTs ssss The dddd is a 4 bit number, interpreted as register, shift count, or XOP number. Finally 6 bits for one general source operand. (Note source operand always occupies rightmost bits!) 2 + 1 + 3 + 4 + 6 bits = 16) Format II has 3 leading zeroes. 16 opcodes identified by first 8 bits. Rest is an 8 bit offset: 0001 xxxx Jumps and CRU single bit 0001 1111 TB 0001 1110 SBO 0001 1101 SBZ 0001 1100 JOP 0001 1011 JH ... 0001 0000 JMP (Notice that from xxxx, the CRU bit instructions are easy to separate. Jumps that test status bits have some 1s. Plain JMP has zeroes. For jumps, you could easily write out sum-of-products equations of the xxxx bits and first 5 register bits. Leading zeroes concept continues thru the end of instruction set. 4 zeroes is Format V: Shifts : SRA ... 5 zeroes is Format VI: CLR, BL, ... 6 zeroes is Format VII: LWPI,RTWP and VIII LI, CI,... 9995 and others have: 7 zeroes is MPYS,DIVS 8 zeroes is LWP, LST Observation: the E/A Roman numeral is approximately the bit position of the first 1. Swap Bus The Byte variant of Format I causes the "Swap Bus" to meddle with the byte order of operand values. On their way between memory, ALU, then back to memory, they either sail through or get swapped as needed. It's like Scylla and Charybdis. Swap Bus The "Swap bus" is just more silicon control lines to multiplex the bytes into the left byte! The "Swap Bus" is 16 2-input multiplexers between the ALU and memory data register. (Abbreviated MD or MDR.) Byte Swap isn't an extra clock cycle--it's just gates switched on or off as the value moves across the swap bus. On the other hand, microcode for SWPB needs to tell it to swap on the front half, not the back half cycle. (Otherwise SWPB is like MOV!) Memory -> MDR > Swap -> ALU B -> (no Swap) -> MDR -> Memory. TL;DR again. Even more concerning microcode: As said above, the number of leading zeroes selects the "entry point" to the CPU's control ROM (microcode) for an instruction group having the same operand decoding steps. Again, the "BYTE" bit isn't up front in the instruction, so it can't affect the entry point. Control ROM is an array of silicon lines which pass across all other functional blocks of the CPU. A group of lines is like a punched card that turns on or off all the functional units of the CPU. Some lines are for the first 1/4 or 1/2 of the cycle, some for later. (One clock cycle is really 4 internal clocks, and 4 steps is enough to: 1. Compute address by adding two things like WP + Rx 2. Set the memory bus address 3. Strobe Read or Write signal 4. Capture read word internally Format I has activated one chunk of microcode, which does the work for two general operands. Microcode for One-operand format , like Format III, would decode only the source field general operand. Observe why the general dest field comes before the source field. Instructions with more bits in the opcode will eat up Td, then dddd. But general source can stay in a common field. Decode general source could be a "subroutine" saving a lot of silicon space! (There might be other tricks.) The location of source bits remains the same down to the instructions that leave just 4 bits for an operand! Of course in single general (CLR) or immediate register (AI) formats, the "Source" is also a destination. LI seems to be a special case! ALU Microcode ultimately sets up the ALU with input operands A and B, and an operation code. SOC 111 B = B OR A MOV 110 B = B A 101 B = B + A C 100 B = -B + A (set status) S 011 B = -B + A (huh?) SZC 010 B = B AND NOT A NEG ???? B = -B INV ???? B = NOT B ABS ???? this one has microcode SETO ???? B = FFFF SLA ???? While(SC--), multiplex B bits from left or right neighbor bit etc A full set of 9-bit operation codes is known for the 990/12 and the ALU chip 74S181. See Bipolar Microcomputer Components Databook. A set of 16 operation codes suffices for the 74LS181 ALU, a really common chip. See any TTL data book. Historical Note: extra adders In drafts of the schematic for the 99/5, a memory mapper used a set of 181s to add logical address and a base address. 171s used just for the add operation! A 16-bit adder allowed any 32-byte boundary. (seen in first draft of 99/5 from Ron Wilcox to Don Bynum.) In the 990 memory mapper, a 16-bit base address was also shifted left 5 bits then added to the logical address. This selected any 32-byte boundary for 2 megabytes max. ( The 990 supported 3 "segments" where one of 3 base address registers was added to the logjcal addresses. So a program segment could be mapped from any RAM address to any logical start address. You might have two shared code segments and a data segment.) The 32-byte unit in a proposed home computer would match the 990 minicomputer exactly. Except in the home computer, the 64K would be divided into 32 little 2K windows. instead of beginning at 2K page boundaries. Four extra 181s would be pricey for a home computer. The 181s were eliminated after a first draft for a 9&/5. To be absorbed into the 99/8 mapper chip.

My XDS/22 (1988) supports TMS34010 emulator. I heard back from the engineer, Douglas Deao, (patents link) that the 34020 was supported in one new system, XDS500, an ISA card with PC hosted software. XDS500 drivers were unique in supporting the 34020 chip's MTAP boundary scan protocol.* The next tool, XDS510, was produced by Spectrum Digital for Texas Instruments. It has drivers for TMS320C2x and C3x DSPs, but not the TMS34020 graphics processor. It's too bad, because the MTAP protocol is used in both 34020 and 320C25 which likely share the same 14-pin header. And the XDS510s are abundant (if not cheap when complete.) Texas Instruments still uses the "XDS" trademark for debuggers/emulators. * MTAP links to follow