FarmerPotato

Wow From the CB Wilson collection, the CC-70. Asking $2500 http://ebay.ca/itm/203128653296?ul_noapp=true

I made an interface on the side port to serialize bus signals into an FPGA (you saw me debugging it...) I got it down to 16 lines. I compressed the address and control lines (24) into 8 lines. The bi-directional data bus I left as parallel 8 lines. So the whole thing fit in 16 lines of the FPGA. A full 4A interface would have taken 34. Here's the breakdown: I connected the 4A address bus to 2 8-bit shift registers, LVC165. An FPGA clocked these registers at 25 MHz. I tried for 50 MHz but it was not reliable. Thus, it took 8*40 = 320ns to read the two shift registers. 3 lines were required for this. Since the 4A external memory cycle is 1000ns, this was fast enough. Legal combinations of control lines RESET, MEM, DBIN, WE, CRUCLK, CRUOUT were encoded by a CPLD into a 3 bit state (reset, memory address, memory read, memory write, cru read, cru write 0, cru write 1) I used 8 bits for the bidirectional data bus. The last two were for A15/CRUOUT and CRUIN. A15 served two purposes: CRU and refining the memory access state. CRUIN was gated onto the bus during cru read state only. This crazy project consumed most of my hobby time in 2018 and was ultimately not super great. I was able to read/write from external RAM, using test programs in Mini Memory. I started to try out a SAMS type pager. But every now and then it would glitch on the odd byte or something. OLD CS1 got me thinking of gigabit ethernet. I didn't think it would work out -- would you have a transceiver at each end constantly updating state? My device reacted to state changes in 10-20ns.

You might have seen Google's "AI Generated Art". This stuff is similar, but you get to tell the AI what to visualize! The research was in the direction of training the AI to fill in the missing word, based on the picture. For example "two people sitting on the ___ playing video games" (couch) This experiment reverses the direction - the AI dreams up the picture from the words. https://vision-explorer.allenai.org/text_to_image_generation Here's the article I saw it in: https://www.technologyreview.com/2020/09/25/1008921/ai-allen-institute-generates-images-from-captions/ For example, try typing in: "a TI-99/4A computer sits on the couch with a cat" The image shows parts of the AI's neural network that (in the past) have trained to recognize images of cats, computers, and couches. It's all blurry like a dream. Obviously, it has been trained on a PC, a brown couch, and a tiger cat. In a world where everybody wears blue jeans. If you say "two people sitting on the couch playing video games" you get... something like that. If you say "two people playing video games", the people are standing up. But the couch is still there, because the AI has been trained that a couch is a typical background in those situations. This infamous phrase from TI's Magic Wand Speaking Reader "mix and match sentences bar codes poster": "Ronald Reagan ... played Footsie ... with Bo Derek ... on the subway". Ed McMahon played that on the Tonight Show. It got a stern letter from the White House! (My dad has a mounted poster of Ed McMahon holding a train, with a bar code that plays a choo-choo train accelerating. It came with a copy of that letter. You can type "chuff chuff, chuff chuff" in TE2 text-to-speech to approximate the Tonight Show performance.) If you take out "on the subway" it is more like the PGA. I tried some Story Machine phrases to see how things have changed in 40 years. (Go play the 4A cartridge, if you have never seen it.) "the tree eats the apple" "the boy dances" "the tree walks to the house" "the tree sits on the house" "the boy runs around the girl" Hmm. Back on testing the range of this thing: "a snake meets a cat" I can't tell if it's the stripes from the tiger cat or from a snake. I thought I got some good Python scales yesterday. "a huge snake killing a small mouse" is better. "one celebrity in the mall" gives someone like Obi-Wan Kenobi in front of a crowd in a trade show. "a droid in the mall" "a spaceship in the mall" "a spaceship in space" "a spaceship in Florida" reveals something like the Space Shuttle carried on the back of a plane. I guess that's what it trained on. "Darth Vader on the death star" is weird: a rose, stained glass, darkness, a CRT "a spaceship with a rose" is improved by saying "a large spaceship with a tiny rose" "a cow eats the grass" is passable "a snake rides on a plane" seems to go back to that Space Shuttle image "the president has a big case of coronavirus", and variations, shows that it knows about the beer. I suspect faces were always blurred out during training. "a big case of coronavirus" reveals the beer. "Ruth Bader Ginsburg at the supreme court" gets you a big audience at a tennis match. "make big money in the valley" still foils my attempts to see if it understands "apple makes computers in silicon valley". It does look like California though. "it is nighttime in the valley" turns out the lights. " a cowboy runs on the grass" gets you the cowboy doing nothing. He can do a lot of other things though. Sometimes it makes a cow-horse. "a cowboy on a horse in the valley" looks like a rider on a cow, but the scenery is improved. I'm amazed how it gets the foreground and background to change across the sentences. It gets better the more specific you are. It would be interesting to know if the AI can reverse the process: identifying the objects it put into the pictures.

Is there a wiener dog program for TI BASIC? You know, the kind where you tell it to print a wiener dog that is X feet long.

I see that too. There are 256 of the 4K angle_ arrays. Each contains single and double arrays taking up 1024 uint16_t. There are 4 of the 8K track1_png_ arrays. So 1MB + 32K.

FinalGROM will be a nice way to run on a standalone console-- but you will need the 32K sidecar anyway unless your code executes out of ROM and doesn't need that 32K of RAM. I think that a 32K/TiPi will be the easiest way to develop. You can use the xdt99 assembler, or gcc, on the Pi. The TI-99/4A will see the output file in a directory. Developing on the 4A console with a Nano is quite authentic, but it is so slow. Serial transfer is ok to a Nano, but I end up just moving the Nano's physical CF card back and forth to a PC. If you meant serial data from the camera? practical baud rates top out at 9600, what rate do you need to grab the frame buffer (or part of it)? (My experience is with the CMUCam and an FTDI interface.. that was 115200) There is also the UberGrom, which provides a UART (on an AtMega.. you might find that useful itself) Some baby steps in interfacing: The cassette port and joystick ports can be exploited. The cassette motor control pin is good for turning a relay on or off. The audio in gate is another - I once sampled this to get entropy in. You can make a serial interface using the joystick port, known as JoyTalk / JoyPrint

TI writer and Editor Assembler. There’s a thread somewhere.

apersson850 probably knows all this but I thought I'd point out: PDP-11 and 9900 are both 16-bit memory-to-memory architectures, and the instruction sets nearly line up. Each has instructions that fit into 16 bits, with the first 4 bits decoding to the general 2-operand memory-to-memory instructions. But PDP-11 has 8 registers, so 3 bits for addressing mode and 3 bits for register#. 12 bits for 2 general operands. 9900 has 16 registers, so 2 bits for addressing mode and 4 bits for register#. 12 bits for 2 general operands. To get 4 more addressing modes, you'd have to give up 8 of 16 registers. Since R11-R15 sometimes have special purposes that is not a nice tradeoff. PDP-11 has ALWAYS special purpose registers R6 stack pointer, R7 Program counter. ---- The PDP-11 16 bit instruction word for MOV is a lot like 9900. And it is quite elegant in octal (3 bits per digit, 6 digits hold 16 to 18 bits) Yes, PDP-11 favors octal. 2 general operands: (byte-flag 0 or 1) opcode Ts S Td D (each field 3 bits except bflag) MOVB has the byte-flag set. Octal, Hex 010000 >1000 MOV R0,R0 11010F >53C2 MOVB R15,R1 see how the fields line up neatly because an octal digit is 3 bits. The leading digit is just 1 bit of a 16 bit word. In 9900 opcode (4 bits, byte-flag last) Td D Ts S (Ts,d are 2 bits, S/D are 4 bits. destination comes first.) >C000 MOV R0,R0 >D04F MOVB R15,R1 For a full comparison of all the 9900, general 2-operand instructions: op instruction. op is 4 bits, +1 if Byte 4 SZC 6 S Six=Subtract 8 C A A A=Add C MOV E SOC 0 other opcodes are built on this, like COC 2 other opcodes are built on this On PDP-11 the 4-bit opcode equivalents are PDP-11 9900 version 1 MOV MOV 2 CMP C 3 BIT COC (but COC is not a general 2 operand instruction) 4 BIC SZC 5 BIS SOC 6 ADD A 7 SUB S +8 if byte There is no equivalent of AB, SB, which would be at hex E and F. the opcodes there are decoded into further instructions. Another big difference is that PDP-11 byte instructions operate on the lower byte! And they are sign-extended. So, memory-to-memory architecture ends up looking quite similar across the two CPUs.

Here's another example of an On/Off switch that is very smart: https://hackaday.com/2020/09/23/teleconferencing-like-its-1988-connecting-vintage-hardware-to-zoom/

If it had 8K of RAM built in at >2000, and the 9940 had made it in, it would be the equivalent of a ColecoVision. But all told, it cost so much more.

Haha. Stringy floppy! I have seen one in use on a Sinclair. No I mean the thing he describes as a TI-88 (calculator I assume), possibly hacked into a prototype cassette thing.

I thought this was beautiful It's a ZIF socket made by TI in Japan in 1990. And here is the lot it belongs to: https://www.ebay.com/itm/99-Lot-Texas-Instruments-TI-CPL044-003-44-Pin-PLCC-Burn-In-ZIF-IC-Socket-Japan/293028064576 And here is a drawing that shows it's TI, otherwise it might as well be Yamaichi It has the nice part number of CPL044-004A I won't be bidding on it, since I only need one part!

D Did I miss some auctions? What I see right now is the Wafertape drive and a cassette prototype (not sure what its for)

Is that a HexBus disk drive being used to prop it up?

In the 80s, I had modems come and go. The nicest I ever had was some 1200 Hayes clone from the cheapest seller in Computer Shopper, and it got fried after a year while replacing the reed switch. In 1988-89 all I had was an acoustic coupler, a Novation "Apple CAT", 300 baud. Fortunately, I had a big rotary-dial desk phone from a garage sale. I used the Apple CAT for almost a year with Telco. It was OK for BBSing, not so great for logging into the local free telnet/ftp gateway to get files. In college, I had a 9600 serial line to my dorm, for which Fast-Term was expressly designed. So I forgot about modems for a while, until I moved off campus. But I still have that CAT and a TI acoustic coupler.

This is not a 9900 instruction, but, the idea you had is provided in the 99000 instruction Branch Indirect. Suppose R14 is your stack pointer: * Pop stack, return to address fetched from *R14 BIND *R14+ The opposite is: * Push stack, Call routine BLSK R14,@VMADDR * does a DECT R14, then push NEXT onto *R14 NEXT ... VMADDR ... BIND *R14+ * return I first learned the concept from PDP-11 assembly, which allows "deferred" or double indirect, with + or -, on every operand (they have 8 registers and 8 addressing modes). If interested go here. Jealous.

Hi, Like apersson850 said, you want these routines to be as fast as possible. Instead of using a stack and VMADDR subroutine, inline the VMADDR in every place it is used. It's just 4 instructions. Then you don't need to save the return address because there is no inner BL. Like you said, if R0-R2 are just for vdp, you can have the caller assume they are used up. If you can have your WS in PAD, then put VDPWD in a register for another speedup. From slow RAM, it takes the CPU 12 cycles to fetch the VDPWD address after the MOVB, but fetching it from a register in PAD takes 2. For VMBW, that's a big savings in each loop. MOVB *R1+,@VDPWD * or LI R15,VDPWD * once MOVB *R1+,*R15 You can go further with inlining. If you know that the length R2 is a multiple of 8 you can inline this: SRL R2,3 * divide by 8 LOOP MOVB *R1+,*R15 MOVB *R1+,*R15 MOVB *R1+,*R15 MOVB *R1+,*R15 MOVB *R1+,*R15 MOVB *R1+,*R15 MOVB *R1+,*R15 MOVB *R1+,*R15 DEC R2 JNE LOOP There is a trick to deal with leftover 1-7 bytes, but I find that most of the time I am writing chunks of 8,32,128,768 and so on.

This was a great game when it arrived, though it is a lot like Tombstone City with interesting maps. I never knew the ad was such nonsense, but surprise, the Normans were descended from Vikings so where is this castle exactly? England (conquered by the the Norman Invasion) or Normandy? (conquered by Vikings who were known as Nor'men). And how did this king learn Ninja arts when a Norman king was lucky to have even read military strategy in Caesar's Gallic Wars? (ie read about the prior Roman invasion of their Normandy... or England...) He must have got a scholarship from Charlemagne to go look for ninjas on the Silk Road, maybe even have come across Buddha or Zoroaster on the way. Uh-huh. Anyhow, fun times.

Seen on Hackaday today "Biometrics is the cryptology equivalent of printing your SSH private key on your forehead"

The package of TIjDINGEN arrived today, full of water and soaking wet. Amanda said: to be fair, it did cross the Atlantic Ocean. Fortrunately, Ciro wrapped the magazines in bubble wrap! They were dry and unharmed. Yay!

Fantastic! I don't understand how the colors stay the same? Do they change after the patterns scroll 8 pixels?

I don't think it's great at emulation. I thought jit was for making threaded code, while non-jit meant a decoder/dispatcher? I think it would be better to add some registers to the stack machine, because emulating a CISC or RISC you know you need a PC, ST, WP, register file, parking for src/dst address/values etc. J1 also doesnt keep an overflow bit in the alu, and you'd need that. I would implement a generic cpu with those features, then write decoders to emulate all the target cpus. So I started some j1 code to emulate the 9900 decoder/dispatcher. I made the PC always at the bottom of the stack. I use 'tbl' to jump to 6 of the Format 1 instructions, Nxxx with 6 bit src/dst addr modes. ( -- d PC+2->PC ) : [email protected] pc @ @ swap 2+ pc ! ; 8000 h# 0000 pc 6x01 @ T'=[T] ( a -- a a ) 6x00 @ T'=[T] ( a a -- a d ) 6x80 swap T'=N T->N 8002 h# 2 6x03 + 7000 h# 0000 pc 6123 ! N->[T] 6103 drop ( in no particular top-bottom order ) [email protected]+: 8002 h# 2 6200 T'=T+N ( next PC ) 6180 swap 7c00 @ ; : init h# 0 ( pc ) run ; init: 8000 h# 1234 ( entry point ) 0xxx jmp run : run do [email protected]+ decode loop ; run: 8002 h# 2 ( inline [email protected]+ ) 6200 T`=T+N 6180 swap 6c00 @ 4xxx call decode 0xxx jmp run ( d -- d ) : decode ( switch: jump into tbl1[n], where n is top 3 bits ) 9000 h# e000 6600 inv 6300 and 800c h# 12 6900 >> 800x tbl 6200 T`=T+N 6143 >r 700c exit ; tbl1: 'decode0x ( many more opcodes ) 'decode2x ( many more opcodes ) 'szc 'sub 'cmp 'add 'mov 'soc ( general src and dst addressing mode decoders ) : gad ( inst -- addr dst inst ) ... ; : gas ( inst -- src inst ) ... ; : mov gad gas ( inst -- addr dst addr src inst ) h# 1000 and ( drops the inst as a side effect ) jz word ( handle a byte operation by testing src and dst address lsbit ) ( do shifty stuff ) ( do masky stuff ) and .. and .. or swap ! ( don't drop ) status exit word: nip nip swap ! ( dont drop ) status ; : status ( d -- bbbb->ST ) ( compare to 0 and set all the status bits ) ; mov: 4xxx call gad 4xxx call gas 9000 h# 1000 6303 and 2xxx jz word ( stuff happens if byte ) 6123 ! 0xxx jmp status word: 6003 nip ( ignore src ) 6003 nip 6123 store 0xxx jmp status : add same as mov but replace "nip nip" with "nip +" : sub same as mov but replace "nip nip" with "nip inv 1+ +" 6003 nip 6600 inv 8001 h# 1 6203 T`=T+N 6203 T`=T+N : cmp cmp is a holy terror cmpb is even worse ; : szc same as mov but replace "nip nip" with: "nip swap inv and" 6003 nip 6180 swap 6600 inv 6303 and : soc same as mov but replace "nip nip" with: "nip or " 6003 nip 6503 or

And see the citations of earlier, bigger stack machines, in https://www.excamera.com/files/j1.pdf b16-small has 5-bit instructions packed into 16 bits, for 3 execution units. How cool is that? There is a 32-bit j1b and a multi-core j4a in the swapforth repo. The j1a fit in 5K of ram on the ice-1k. I wrote my sd card driver on that one before the other 3k filled up Now I'm running the mecrisp fork of j1a, where Matthias optimized, put the barrel shifter back in and added mpy, on ice-4k. It's my favorite hardware tester, for my V9958 board. Bowman's j1a left opportunities for optimizing because it coded so much in FORTH, not assembly. OK, now about emulation..

I was motivated to try some hand-assembly in J1 assembly language, and share the love for this little cpu. So, here is sex (sign-extend) for the J1. The J1 is a stack-based machine, similar to the Novix NC4016, with an instruction set designed to run FORTH. Read about it here: https://www.excamera.com/files/j1.pdf or https://excamera.com/files/svfig-2015-aug.pdf Its opcodes are: 8000 push 15-bit literal 3-bit opcodes with 13 bit arguments: 0000 jump 2000 jump if zero 4000 call 6x00 ALU. The bit fields are like microcode. x is an operation from 0-f , for example T+N, ~T, fetch [T] or NrshiftT So, let's do it. Sign extend the high byte of the 16-bit word at s1. ( w0 s1 -- [s1]>>8 -> [w0] ) : sex @ h# 8 NrshiftT h# 80 N<T jz done h# 00ff inv + done: swap ! ; assembled: sex: 0000 6C00 @ 0002 8008 h# 8 0004 6903 >> 0006 8080 h# 80 0008 6803 N<T 000a 2009 jz done 000c 80ff h# 00ff 000e 6603 inv 0010 6403 or done: 0012 6180 swap 0014 6123 N->[T] drop 0016 710f drop ; Of course, in FORTH, you wouldn't write sex as a memory-to-memory operation. It should just be a stack operation. Once sex is defined in the dictionary, calling it is one instruction. See the full listing at the end. Some curiosities: 1. The opcode 8000 pushes a 15-bit literal to the stack. To load the 16-bit value ff00, it is necessary to push 00ff and invert it. 2. ! must consume 2 values from the stack, but one ALU cycle can drop only 1. So I insert an extra drop. If you want to leave the value on the stack, you can get that for free. The idiom "dup addr !" can be optimized to "addr N->[T] drop", fitting in two instructions. 3. ; is usually free - You can do an ALU operation to the stack, and also pop the return stack and return. This: 000b 6103 drop 000c 700c ; To optimize, you may OR the instructions for the combined effect, because the CPU units are independent. 710f operates on the data stack, return stack, and PC. 000b 710f drop ; 5. [email protected] is messy. Addresses are byte-oriented, but memory access is aligned to 16-bit words. Sound familiar? The J1 has no "MOVB" only "MOV". Where @ is one instruction, [email protected] is written in software, and must check if the address is even or odd, then shift or mask. Full Listing : [email protected] ( addr -- c ) ( little endian ) h# 1 TandN jz ceven h# 8 >> ret ceven: h# ff and ; : sex ( c -- d ) h# 80 N<T jz done h# 00ff inv or done: ; 0 variable w0 0 variable s0 : main w0 [email protected] sex s0 ! ; [email protected]: 0000 8001 h# 1 0002 6300 TandN 0004 2005 jz ceven 0006 8008 h# 8 0008 790f >> ret ceven: 000a 80ff h# ff 000c 730f and ret sex: 000e 8080 h# 80 0010 6803 N<T 0012 200d jz done 0014 80ff h# 00ff 0016 6603 inv 0018 740f or ; done: 001a 700c ; this word could be optimized away w0: 001c 8020 h# 0020 001e 700c ; 0020 0000 s0: 0022 8026 h# 0026 0024 700c ; 0026 0000 main: 0028 400c w0 002a 4000 [email protected] 002c 4007 sex 002e 400f s0 0030 6123 N->[T] drop 0032 710f drop ;

Has anyone done this before? Would it work? Two pages of partial bitmap mode, swapped by changing VR3 and VR4. The idea is to use a pattern table mask, restricting it to the 1st third only. The pattern table is filled with F0, which gives fat pixels, like in Rasmus' Raycaster. The color table is as usual. However, the top third of the color table is static, filled with F0. The other 2/3s are what is updated on each frame. To flip pages, you swap the pattern and color table addresses in VR3 and VR4 (leaving masks unchanged.) This gives you two buffers for the bottom two thirds of the screen. The top third is, alas, transparent and white bars--so set the screen color to white. There is no way to reserve part of the pattern table for alphanumeric patterns, because it would double as its own color table. You could however cut off 2 columns, reserving 16 chars. Make one solid, one transparent. Use this to blank out the top third, and sidebars. You could draw block letters or numbers in white and transparent. You can still define all the sprites. Am I understanding the undocumented modes correctly? VDP memory map 0000 F0 0800 color for page 1 middle third 1000 color for page 1 bottom third 2000 F0 2800 color for page 2 middle third 2000 color for page 2 bottom third Reference: http://www.unige.ch/medecine/nouspikel/ti99/tms9918a.htm#hybrid bitmap