FarmerPotato

I have wondered if anyone still makes extra wide space bars.

I didn't notice on my own, but Erg titles it "EIA Colors" so there you go.

In the old days, a wave soldering manual called for chips to face their prow into the wave, rather than get hit broadside. Arrr.

Another interesting offshoot was Lilith (1976). Niklaus Wirth was at Xeroc PARC in 1976 and used the Alto. On returning to ETH Zurich, he had a small team create a "desktop workstation" by 1980. It's really interesting reading, how Wirth re-created the Alto concepts in the Lilith workstation, starting with a very large bitmap display. This article claimed about 310 in use.

I last got wires from Pololu They only have 7.5 cm female to female But other kinds are in sizes down to 5 cm

Originally documented in Shugart manuals, for instance SA-850 drive. The allocation bitmap rules in 99/4 Disk Interface are the same as you'd find in other 990 operating systems. Under Floppy Disk Physical Format, in TX990 and DX10 Systems Programmer Guides. Except that the allocation map was spread over many sectors of track 0, supporting 1.2 MB floppies. Weirdly, AU size could be 1 sector or a multiple of three.

I browsed slide switches at TEDSS.com: page 5 shows an ERG 10-DIP for $10. Website says that they "cater to hobbyists" and "hard to find parts". For this pricing, there is a minimum $20 per line item (so two switches) and $40 minimum order. I could see using a color 2-switch in place of 2 jumpers. For instance BlackIce has a DFU mode jumper next to a serial port enable jumper--not labeled.

Thanks @acadiel . So it's an Erg. Seems they have the category to themselves. And a minimum of $3 per switch is pricey.

Noticed them on Stuart's photo collection!

I first saw the 99/4 in about December 1980. It was an Open House event for families at the Texas Instruments plant in Lubbock TX. Then, the hottest TI product was the Digital Watch with calculator built-in. Coming in second: must have been the helium balloons. Next to the digital watches was a 99/4 (no A) display and a crowd of people. They were waiting to play 'Pot Shot' from the Video Games I module. This was the store display, with modules on retractable steel cables. We got watches for Christmas. I was in 4th grade. My dad brought home a 99/4 in March 1981, from the Texas Instruments employee store. We used our cassette deck for everything. For software, we had 'Oldies but Goodies 2' and 1 module, A-maze-ing. Our dad said 'now learn to make your own software.' So we did. I think we got Hunt the Wumpus and MunchMan in 1982. I didn't see a 4A until Sep 1982, when Texas Instruments loaned 2 systems to our Boy Scout troop. (Both of the Scoutmasters were from Texas Instruments.) 4As with the sidecars for disk and 32K. Each Scout got one Inmac floppy disk. The conditions were: we all had to earn the Computers merit badge and put on a big demo at Jamboree. We kept a 4A at home until Black Friday... when Texas Instruments said "no need to return them". By then, I had spent hundreds of hours programming or typing in programs. 4A was my only computer thru 1988, when I worked all summer to buy a Geneve 9640. Used that until 1992! Still have a place in my heart for those sidecars. The 4A with the loan sticker turned up in the basement yesterday.

eBay's automatic "Inspired by your recent views": What I actually viewed: Texas Instruments Color Graphics Board RARE What it said I should look at: Cray X-MP Memory Board The Color Graphics Controller Board works with TIPC or IBM PC. It is based on a TMS34061 display controller with 256KB of VRAM. (4 banks of 8 TMS4161 64Kbit dual-port). The output is 1024 x 512 display in 4-bit color. The DE-9 port is for an EGA monitor - digital output in 8 colors. A 2nd version of this board would have a TMS34070 palette chip, providing analog output with 16 colors per row (18-bits per color). I thought of it as an evaluation board. Wonder if any TIPC software drove it. The Cray X-MP Memory Board works with... a Cray X-MP. See those QUAD INLINE PIN chips? Those are MECL-to-TTL translators, to isolate noisy TTL circuits. MC10125 type. MECL is a differential signal with + and - traces (like USB D+ D-). RAM is MCM6287L-35. Fast 35ns access time, 64Kbit each. Total 256K x 9 (parity).

I want to start a thread where we can help each other find obscure parts. It can be a fun game, maybe you even need the part for a project. I will get it rolling: Who made these colorful slide switches, and where can you get them now? (IC included for scale.) Seen on Madge Networks 1987 Token-Ring network card (ISA). Made in the U.K.

TIGraph 100 https://www.ebay.com/itm/143208585595 My hunch is this was made in the 1960s to print manufacturing line data. I guess it counted electrical pulses from the back terminals. In 1961, TI needed real-time charts of how many transistors were falling automatic testing. The Geophysical and Instrumentation Division invented countless machines to automate the production line. (Mike Bunyard got his start there.) See Ed Millis' book: TI, the Transistor, and Me: My Dis-integrated Journey Through Texas Instruments. (It has very funny stories too.)

"to the designers distinct advantage" made sense to me--it was a trade-off. But what did it really mean? According to a Texas Instruments patent disclosure, the 9900 instruction set is decoded by the number of leading zeroes. This number selects the "entry point" to the CPU's control ROM (microcode). For each "entry point", instructions share a common operand decoding. None or 1 is Format I 2 zeroes is Format III,IV,XOP 3 zeroes is Format II etc The "BYTE" bit isn't up front in the instruction. So whether it's 0 or 1, it can't affect the entry point. MOV has the same number of zeroes as A (add) and ADD definitely needs the destination to be read. As a result, all Format I instructions fetch the destination operand, even MOV which doesn't need it. 9995 This CPU doesn't need to fetch or store a whole word if the instruction is a BYTE type. Special case: does MOVB avoid read-before-write. (I think it does?) 99000 The 99000 cpus eliminated read-before-write as a special case for MOV. Register to register MOV takes just 3 cycles, where MOVB still takes 4. (MOV: WR read, AUMS, WR write.) TL;DR Much more than just read-before-write. We're going to decode the 9900 instructions at the bit level. You'll see the leading zeros concept throughout. Format I instructions, A or MOV for example, begin with one or no zero. Format I have general destination and source operands. Two leading zeroes means Format III: one destination register, one general source operand. Format I and III examples MOV 1100 Td dddd Ts ssss MPY (format III) 0011 10 dddd Ts ssss where Ts,Td are: 00 register, RX 01 register indirect , *Rx 10 symbolic @Y(R0) or indexed @Y(Rx) 11 register indirect auto increment, *Rx+ dddd and ssss are register numbers. Some longer tables sorted by leftmost bits, counting down. Format I. One or no leading zero. Two general operands. Opcode is 3 bit ALU operation code, one bit "BYTE" flag. Then 6 bits DST, 6 bits SRC. (Total 16 bits) Opcodes: 1111 SOCB 1110 SOC (set ones) 1101 MOVB 1100 MOV (move) 1011 AB (add byte) 1010 A (add) 1001 CB 1000 C (compare) 0111 SB 0110 S (subtract) 0101 SZCB 0100 SZC (set zeroes) Formats III, IV, XOP have 2 leading zeroes. 0011 xx MPY, DIV, LDCR, STCR 0010 xx XOP, XOR, CZC, COC These are 8 similar opcodes made using 6 bits. 2 zeroes, a 1, then 3 more bits. (2^3 = 8.) Leaving 10 bits for operands. Opcodes have started to nibble at operand fields, eating Td first. Decoding: 001x xxdd ddTs ssss The dddd is a 4 bit number, interpreted as register, shift count, or XOP number. Finally 6 bits for one general source operand. (Note source operand always occupies rightmost bits!) 2 + 1 + 3 + 4 + 6 bits = 16) Format II has 3 leading zeroes. 16 opcodes identified by first 8 bits. Rest is an 8 bit offset: 0001 xxxx Jumps and CRU single bit 0001 1111 TB 0001 1110 SBO 0001 1101 SBZ 0001 1100 JOP 0001 1011 JH ... 0001 0000 JMP (Notice that from xxxx, the CRU bit instructions are easy to separate. Jumps that test status bits have some 1s. Plain JMP has zeroes. For jumps, you could easily write out sum-of-products equations of the xxxx bits and first 5 register bits. Leading zeroes concept continues thru the end of instruction set. 4 zeroes is Format V: Shifts : SRA ... 5 zeroes is Format VI: CLR, BL, ... 6 zeroes is Format VII: LWPI,RTWP and VIII LI, CI,... 9995 and others have: 7 zeroes is MPYS,DIVS 8 zeroes is LWP, LST Observation: the E/A Roman numeral is approximately the bit position of the first 1. Swap Bus The Byte variant of Format I causes the "Swap Bus" to meddle with the byte order of operand values. On their way between memory, ALU, then back to memory, they either sail through or get swapped as needed. It's like Scylla and Charybdis. Swap Bus The "Swap bus" is just more silicon control lines to multiplex the bytes into the left byte! The "Swap Bus" is 16 2-input multiplexers between the ALU and memory data register. (Abbreviated MD or MDR.) Byte Swap isn't an extra clock cycle--it's just gates switched on or off as the value moves across the swap bus. On the other hand, microcode for SWPB needs to tell it to swap on the front half, not the back half cycle. (Otherwise SWPB is like MOV!) Memory -> MDR > Swap -> ALU B -> (no Swap) -> MDR -> Memory. TL;DR again. Even more concerning microcode: As said above, the number of leading zeroes selects the "entry point" to the CPU's control ROM (microcode) for an instruction group having the same operand decoding steps. Again, the "BYTE" bit isn't up front in the instruction, so it can't affect the entry point. Control ROM is an array of silicon lines which pass across all other functional blocks of the CPU. A group of lines is like a punched card that turns on or off all the functional units of the CPU. Some lines are for the first 1/4 or 1/2 of the cycle, some for later. (One clock cycle is really 4 internal clocks, and 4 steps is enough to: 1. Compute address by adding two things like WP + Rx 2. Set the memory bus address 3. Strobe Read or Write signal 4. Capture read word internally Format I has activated one chunk of microcode, which does the work for two general operands. Microcode for One-operand format , like Format III, would decode only the source field general operand. Observe why the general dest field comes before the source field. Instructions with more bits in the opcode will eat up Td, then dddd. But general source can stay in a common field. Decode general source could be a "subroutine" saving a lot of silicon space! (There might be other tricks.) The location of source bits remains the same down to the instructions that leave just 4 bits for an operand! Of course in single general (CLR) or immediate register (AI) formats, the "Source" is also a destination. LI seems to be a special case! ALU Microcode ultimately sets up the ALU with input operands A and B, and an operation code. SOC 111 B = B OR A MOV 110 B = B A 101 B = B + A C 100 B = -B + A (set status) S 011 B = -B + A (huh?) SZC 010 B = B AND NOT A NEG ???? B = -B INV ???? B = NOT B ABS ???? this one has microcode SETO ???? B = FFFF SLA ???? While(SC--), multiplex B bits from left or right neighbor bit etc A full set of 9-bit operation codes is known for the 990/12 and the ALU chip 74S181. See Bipolar Microcomputer Components Databook. A set of 16 operation codes suffices for the 74LS181 ALU, a really common chip. See any TTL data book. Historical Note: extra adders In drafts of the schematic for the 99/5, a memory mapper used a set of 181s to add logical address and a base address. 171s used just for the add operation! A 16-bit adder allowed any 32-byte boundary. (seen in first draft of 99/5 from Ron Wilcox to Don Bynum.) In the 990 memory mapper, a 16-bit base address was also shifted left 5 bits then added to the logical address. This selected any 32-byte boundary for 2 megabytes max. ( The 990 supported 3 "segments" where one of 3 base address registers was added to the logjcal addresses. So a program segment could be mapped from any RAM address to any logical start address. You might have two shared code segments and a data segment.) The 32-byte unit in a proposed home computer would match the 990 minicomputer exactly. Except in the home computer, the 64K would be divided into 32 little 2K windows. instead of beginning at 2K page boundaries. Four extra 181s would be pricey for a home computer. The 181s were eliminated after a first draft for a 9&/5. To be absorbed into the 99/8 mapper chip.

My XDS/22 (1988) supports TMS34010 emulator. I heard back from the engineer, Douglas Deao, (patents link) that the 34020 was supported in one new system, XDS500, an ISA card with PC hosted software. XDS500 drivers were unique in supporting the 34020 chip's MTAP boundary scan protocol.* The next tool, XDS510, was produced by Spectrum Digital for Texas Instruments. It has drivers for TMS320C2x and C3x DSPs, but not the TMS34020 graphics processor. It's too bad, because the MTAP protocol is used in both 34020 and 320C25 which likely share the same 14-pin header. And the XDS510s are abundant (if not cheap when complete.) Texas Instruments still uses the "XDS" trademark for debuggers/emulators. * MTAP links to follow

Fascinating blog. I went down several links after the TOD part.

Yay! Laser PCBs! I once hoped that the laser precision would allow for prototyping finer traces. But in my experiments, I only got as far as a working 1-sided Arduino with 0.1". What etch process did you use? I found the "regenerating copper chloride" process quite efficient. Vibrate the solution every minute or so. I see you etched away a large area. I would try to minimize the copper being removed. That conserves your solution. Another trick that I liked--if you are rasterizing a design, is to burn vector outlines of the traces. It looks like you hit upon a good paint for this. My friends and I tried a bunch of spray paints before getting one that stuck well all through the etching. Have fun with your laser! I know you are creative and persistent!

Sounds interesting (I'm not familiar with NC.) Try it out? But if it's longevity we need, we oughta consider a long term hosting, like Lizard Hill (WHTECH.com) or pair.com or whichever.

I agree with this as a noble sentiment. But supposing we all raised the money the retiree wants and deserves, there's still so many problems. Who's had the time and interest to look at 980/ 990s already in museums? We must be the last generation with the passion to do anything with it. Maybe some distant future researcher will have a need for research. (Assuming museums don't dispose of it.) But right now, that's us amateurs. Lot of feelings.

Thank you Gary, the blog gives me a much clearer idea how teletext came together. Colin Hinson's blog describes using (and inventing!) the particular assortment of Teletext and 9995 boards that Stuart is listing... I've wanted to know more about the Bedford office. The blog writing is vivid. TIdings, Bedford's site newsletter, is listed for 1979-1982 in the Texas Instruments Records at DeGolyer.

Curious about the several Teletext boards shown. They show the TMS3556, a versatile VDP ideal for showing text in multiple colors. (Used in ExelVision) I found a mention of Teletext chip sets from French companies RTC (Phillips), EFCIS, and Texas Instruments France. Prepared for the Antiope teletext system. Teletext was/is digital data piggybacked onto the analog TV signal.

Some bits about the /1481 and the /306 Speech Board in Electronics. I hunted through the 1980 issues. Also found a block diagram for the 1481 -Osborne book probably taking after the Microsystems Handbook. Another item describes the Analog Devices ATE (automated test equipment) for linear ICs, as a TM990 floppy based system. Could that 16-slot rack be related? Bunch of Analog A/D boards there. Thread: "Working with a TM990/100 or 101M CPU, the new TM990/306 module can verbalize 179 words, including 0 to 12 and A to Z." [Electronics, Mar 27, 1980, p. 84] and [Electronics, Apr 10, 1980, p.84] [Ads for TM990/306 Speech Module for $1280]

Question about TM990/307 IO ports: Since XDS/22 once had a 307, I want to know the 307's port addresses. (my XDS in 1989 hasnt got a real 307, maybe a hybrid derivative). My guess is: CRU 0000 port 1 9902 9903 0040 port 2 9902 0080 port 3 9903 9902 I had looked at the 990/5 machine but that had a different order. XDS labeled port #3 is the only one fitted in mine. So, it's the user terminal, the host. Host may be CRU 0000 port #1 internally but labeled port #3 externally. The disassembled PRTCHR XOP branches depending on port. Some SBO/SBZ are definitely not for 9902. Guess 9903. It seems to honor outgoing XON/XOFF only on one port. If sending a Ctrl-S (XOFF) it truly zeroes RTSON. Transmitter off. Maybe this is for huge file upload from host. Maybe printing...

Wait, what? The MVP is 320C80? Or the other way round? Another is the TVP4010 and up. These were in late 90s gaming 3D accelerator graphics cards. GLint accelerator. Seems Texas Instruments did make inroads in mainstream graphics cards.

Very! The 990/12 had 64 bit wide microcode for the 481s. Soldered in. I think I see the 1481 with ten sockets? So 80-bit wide. Plus that daughter card... The 1481 is a 9900 built from TTL. Not necessarily the TMS9900 but definitely a family member. With the 1481 microcode ROMs, you'd have a crucial tool to make a 9900 simulator at the silicon level. @mizapf Plenty of difficulties, but maybe Texas Instruments made it fairly close to a documented architecture. I've made notes on what I found so far.