rpineau

I manage to run more test (as did Juliusz) and we now have better result with the 8/32 MHz switching : GEM Bench v4.03 Ω Ofir Gal - 3 March 95 ============================================ Mega STE TOS 2.06 AES v3.20 GEMDOS v0.32 MiNT not present Blitter Enabled NVDI not present Video Mode: 640*400*2 FPU not present Run and Malloc from STRAM Ref: STE + Blitter, ST High ============================================ GEM Dialog Box: 5.485 100% VDI Text: 5.315 103% VDI Text Effects: 10.665 138% VDI Small Text: 5.840 104% VDI Graphics: 11.255 209% GEM Window: 1.530 103% Integer Division: 1.560 1153% Float Math: 10.735 124% RAM Access: 2.945 213% ROM Access: 2.535 248% Blitting: 1.720 106% VDI Scroll: 3.970 107% Justified Text: 5.105 106% VDI Enquire: 2.480 107% New Dialogs: 7.010 108% ============================================ Graphics: 117% CPU: 434% Average: 201% Not a huge improvement but faster is always good. We have a few issues on MegaSTE : If we enable the 16KB cache : freeze When in 8/32 mode when general.cpx switch to 16MHz no cache: freeze. So the switch from 8 to 16MHz on the mother board probably create a glitch. If I set the jumper to directly get sys_clk from the mother board (so no 32MHz switching), the machine works fine and switch ok from 8 to 16MHZ (mother board). As the goal is to run always at 32MHz for the CPU we're not going to spend to much time tracking the issue with 8/32 to 16/32 switching. As for the MSTE cache, I'm still trying to figure out what's going on but I haven't had time to put the logic analyzer on it (may be next weekend).

Juliusz started doing some testing with the 8/32 MHz switching (the end goal is to always be at 32MHz) with good results. He had to use the system 32MHz and not the 32MHz oscillator on the board as the switching between 2 unrelated clocks was causing issue. Here are some result at 8/32 MHz : Blitter OFF : GEM Bench v4.03 Ω Ofir Gal - 3 March 95 ============================================ STE TOS 2.06 AES v3.20 GEMDOS v0.32 MiNT not present Blitter Disabled NVDI not present Video Mode: 640*200*4 FPU not present Run and Malloc from STRAM Ref: STE, No Blitter, ST Medium ============================================ GEM Dialog Box: 6.685 118% VDI Text: 10.610 132% VDI Text Effects: 18.110 133% VDI Small Text: 11.080 122% VDI Graphics: 9.085 208% GEM Window: 2.045 160% Integer Division: 1.575 1142% Float Math: 12.165 109% RAM Access: 3.020 208% ROM Access: 2.660 237% Blitting: 3.430 257% VDI Scroll: 7.145 188% Justified Text: 9.235 149% VDI Enquire: 2.615 101% New Dialogs: 7.840 121% ============================================ Graphics: 153% CPU: 424% Average: 225% Blitter ON : GEM Bench v4.03 Ω Ofir Gal - 3 March 95 ============================================ STE TOS 2.06 AES v3.20 GEMDOS v0.32 MiNT not present Blitter Enabled NVDI not present Video Mode: 640*200*4 FPU not present Run and Malloc from STRAM Ref: STE + Blitter, ST Medium ============================================ GEM Dialog Box: 5.785 97% VDI Text: 5.855 98% VDI Text Effects: 10.010 120% VDI Small Text: 6.635 99% VDI Graphics: 8.845 194% GEM Window: 1.580 100% Integer Division: 1.570 1143% Float Math: 12.145 109% RAM Access: 3.020 208% ROM Access: 2.610 241% Blitting: 1.350 102% VDI Scroll: 4.265 103% Justified Text: 5.555 100% VDI Enquire: 2.610 101% New Dialogs: 7.445 103% ============================================ Graphics: 110% CPU: 425% Average: 194% We think we might have some timing issue on /BR, /BG, /BGACK which might explain the "slow" blitter result (or may be we don't and Gembench timing loop are wrong on a 68020). Rodolphe

Today we had a breakthrough. Even though we still see some issues with the Atmel ATF series (issues with the output enabled of some output when using combinatory equation for these) we got a working proto. All of this thanks to Juliusz who found most of the problem I had (mostly related to the OE issue). He was able to get it working on a STE with TOS 2.06. Here are a few perf he got from Gembench running the 68020 at 8MHz: ======================================== Results (I had blitter on, reference is STE with blitter): Display 95% CPU 164% Average 113% Integer: 284% !! VDI graphics: 126% RAM access: 131% ROM access: 151% All other are about 90-100% With blitter off, reference: STE with blitter off: Display 116% CPU 165% Average 129% Integer div: 285% VDI graphics: 132% RAM: 131% ROM: 152% Blitting: 151% All other slightly above 100% Float: 93% VDI Enquire: 91% ======================================== Now that we have a working version of the code (and a few hardware fixes to go with it) we can move forward and start trying the 33MHz switching on /AS (same as the 68000 booster from exxos). Rodolphe & Juliusz

Quick update : Some tests have been done on a STE and we see a white screen with 20 bombs. So we have almost the same behavior on the STE and MegaSTE. So this is progress in some way.

Quick update : I have been very busy with work and other project in the last 4 weeks so the only thing I manage to do is to build a 2nd card and send it to someone who contacted me and want to help (he got all the tools needed for this). I added a pull-up on A0 (was missing) and on the CPU /BG. I also added 2 electrolytic capacitor (33uF each) on the 5V line. I haven't yet tested this to see if it helps with the weird things we were seeing on some signals. You can also blame the Rugby world cup for my lack of time spent on this Rodolphe

Tekmos is making 68020 cpu mostly for 1 reason .. the US Military. So they might not care about small order like we would need for this card. I can share the files.. no need for github.. just ask. The current files for the CPLD have no magic trick in there so sharing them is no issue I can also share the Eagle schematics and PCB of the prototype (useful for debugging). Rodolphe

I did contact Tekmos .. they never replied. Right now the issue is not funding. I need to figure out why it crash at some point in the boot. What can be done to help ... well .. I would need someone that is better than me at CPLD (not hard to find ), that can work in WinCUPL, can buy the Atmel JTAG programmer .. on my side I would provide a fully populated card for free. Currently I only have the STE/MegaSTE version (with a 68000 PLCC socket). It also requires a TOS 2.06 (for 68020) support. Whoever is interested probably also need a small logic analyser. Rodolphe

This card will plug in place of the CPU. So from a hardware standpoint there's going to be 2 (or 3) version : STF, STE (and may be a specific version for MegaSTE as it has a native 8/16 MHz bus). The main issue for some people will be the space in the machine depending on the mother board revision. Also, you'll need a TOS 2.06 in the machine (people have asked that I don't put a TOS on the board and allow people to do their own TOS 2.06). Right now the card still doesn't work (there is progress.. but still). I didn't have time to work on this for the last 2 weeks so no news on that front. The goal is of course to make it works on as many machine as possible but some motherboard will simply not have the space (specially the one with the STF with CPU close to the floppy). Now depending on the demand I might be able to produce multiple layout and may be do different STF versions. But I first need to focus on getting the logic working first. Once I get a full boot to TOS, then we can look at different layout and optimisations. Rodolphe

So before assembling the other board I'm going to spend a little bit more time on the current one as the issues I see (see http://www.exxoshost.co.uk/atari/last/020BOOSTER/update) might require a new board to fix them. I might also try to find a STE and put a TOS 2.06 on it for testing as the MegaSTE might behave differently in term of signal quality. Rodolphe

Well ... that would not be as fun as making my own Plus I'm not sure we can still find them and even less sure they fit in a MegaSTE I spent about 6-7 hours yesterday trying to debug all of this with MrMartian. We changed the DSACK0 on ACIA access to DSACK1 for all access and that seems to work. BG seem to behave now. I cleaned the 68000 PLCC socket as there was a little bit of corrosion and bent back the pin toward the inside to get a better contact on the PLCC plug. We can see the 68020 starting, TOS access are fine as we can see proper cycle in 4 clock cycle and DSACK1 asserted at the right time. ACIA access looked better at the end of the day (with LDS and UDS at the right level). We still see some weird pulses on some signals (like I saw on BG before) and I think it might be a bug in the logic analyzer software that shows a HI level for a 0.1V signal. Of course if the analog sampling is to slow I might not see a spike (I use a Logic 16 from Saleae). So it still doesn't work but I think we're making progress. Rodolphe

@MrMartian. I can send you the equations as well as the Eagle files. For 8 bit access, the 68020 expect a 8bit device to be wired on D24-D31 (which is D8-D15 of the 68000 bus) and /DSACK0 is used to terminate the cycle. I'll pm you my email so we can talk about this.

What TOS 2.06 supports is a fix for the "move SR, <EA>" instruction that is a user instruction on the 68000 but a supervisor instruction on the 68010 (and up). Also, I have finally received the 2 PLCC68 plug so I can assemble the 2 other board... hopefully this weekend.. if not.. next weekend. Rodolphe

@LynxPro : I too think atari had done some test with the 68020 either in the TT or a new version of the MegaSTE (the MegaSTE was released after the TT as far as I can remember). @Klund1 : No idea yet. The CPLD if fairly cheap (~ $7 for an ATF1504AS PLCC 44), the test board were $85.20 for 3, so $28.40 each (4 layers). The price of a 68020RC33, depending on what you can find on eBay.. about $30. Then there is that damn PLCC 68 plug.. that's the most expensive part.. They are about $39 a piece (plus shipping and taxes). On the dev board I also put an expansion connector (DIN 41612) with all the 68020 signals .. $11, add resistors, caps, headers, oscillator.. that gives a build cost of about $120 so far including the CPU. The board can probably be made for a lot cheaper once I've solve everything and it's working. Right know .. I know the CPU boots, I see a lot of TOS access, I see ACIa access but it crashes after a while and I never get the white screen with the Atari logo. I know that my /AS, /UDS, /LDS signals are fine. I'm fairly sure that my VMA and E signal are also fine as they match what I can see with the 68000. DSACK 1 is definitely working (it tracks DTACK) as the TOS access work. DSACK0 (for ACIA access on 8 bit) during VMA access seem to also work. I know I have a weird issue as the /BG pin coming from the mother bord seem to follow DTACK .. it shouldn't as this is an output pin on the 68000/68020 .. so the issue might be there.. As I haven't seen any logic analyser trace fo a 68020 on an Atari I'm a little bit in the dark. I don't mind sharing all my equations for the CPLD as at this stage it's mostly coming from the Motorola AN944, the LUCAS code and some other code I found left and right. As I have to use WinCUPL for the CPLD, I have to adapt the code I find and there is always a chance of me messing up something. I do intend to finish the project as I want a 68020 in my MegaSTE... as for how long that will take.. no idea. I'm going to assemble a 2nd card to see if I see the same issue on /BG. I also need to order more PLCC 68 plug as well as a few ATF1502 and ATF1504 (same pinout, more MLC in the later so that I can experiment with more stuff than needed and I can trim down later) for the 2nd board (and the 3rd one at some point as I have 3 PCB). The challenge is always being the only dev on something like this. As I do this to learn I'm bound to make error.. and without any input from a team mate this takes a lot more time to get sorted out. Rodolphe

Both

So I check all t he connection.. no short between the ST_BG pin and any other pins.. so no idea why it does what it does even if not connected to anything(see trace on the status page for the "/BG issue" ). For the MegaSTE schematics, the CPU /BG pin is directly connected to pin 9 of U2 (PAL 16R4, input 7). IT probably gets out through one of the output to U11 as the final /BG sent is coming out of that PAL on pin 19 (XCPUBG). SO there is NOTHING connected to this BG pin except for U2 pin 9 and that's an input !!! At this point I'm going to assemble a 2nd board to see if I get the same issue (I took one of the PCB I have and checked for shorts there to incase it could be a PCB manufacturing issue... nothing). Any idea ? Next time I connect the logic analyser to the MegaSTE I'll take trace of these pins with the 68000 in place before removing it to insert my board. I might also make a trace without any CPU to see what's going on. Rodolphe

I did more work on this today. Some good news, I fixed DSACK1 and ACIA access (I think)... and some not so good news as it still doesn't work. There is definitive progress and you can see the update on the status page. Here is a quick picture of the test setup : Rodolphe

The AB project is still on .. about to make new board and rebuild the Falcon, I should also get a Milan 040 to test on it

So I was taking another look at a few of the 68020 board and docs (AN944, LUCAS, ...)... they use PAL16R4. I looked at the equation and basically copied them all in a single file, fix the names to remove unneeded pins and use internal pins of the CPLD. And as you all know.. so far it doesn't fully works... then I went back to the data-sheet of the PAL14R4 .. well well well .. look at that .. pins 14 to 17 are registered output ALWAYS .. which mean I need to recheck all my equation and based on which pin on the original PAL design they were on, make them registered (aka hey go through a D-Type flip-flop clocked by whichever clock was present on pin 1 of the GAL.. in my case the system clock). Sometimes it pays to pay attention to the component and not just the equations. Rodolphe

Quick update. I fixed some equation and I now see what looks like proper access to the TOS. The CPU even runs for 7 full seconds and then /AS stays up and nothing more seems to be happening (I need to add more probe to check for buss error and what not). I even saw what looks like a proper access to the keyboard ACIA by monitoring its CS1 pin and the VPA signal (see traces on the status page). I know my MegaSTE display the Atari logo after about 4 seconds.. so here 7 seconds with a black screen means something is not hapening and the CPU get stuc accessing something.. but what !!! /DTACK is tie to DSACK1 and pretty much follow /AS (/ST_AS). TOS access seem to be fine as I see a lot of them using the ROM /CE pin. Next step will be to make sure /UDS and /LDS are asserted as they should... may be there is a bad bus access and the CPU loops trying to get data from one of the component. If anybody has any idea.. let me know I have 2 more board that I might assemble if some people with a MegaSTE or STE want to help (TOS 2.06 required). I use Atmel WinCUPL with one of their ATF1504 (I have to move to the 1504 from the 1502.. not enough space ) and their USB JTAG cable. Rodolphe

Quick update. I tested the card in the MegaSTE.. and it didn't explode. So at least that's good. But of course it doesn't work yet. I updated the status page with my findings. More test next weekend once I fix more of the CPLD code. I think there might be some error in the Motorola AN944. Rodolphe

The 68020 is directly compatible with TOS 2.06 and the most compatible with the 68000. Also as I said, I'm doing this to learn.. so start small, the build bigger things. The 68030 is more "complicated" to adapt to the 68000 bus and if we want to make use of all the feature including burst memory access, it gets even more complicated. Add to this that it would require a patched TOS 3.06 and this becomes a way bigger project than what I have time for. If someone wants to do a 68030 board, go ahead (Rodolphe Czuba even offered at some point to make a CT2-like card for STF/STE but everybody bashed him ... ). So for now I'll stick to the 68020 which gives me a better chance to actually finish this project then evaluate what's next. Rodolphe

I have been working on a 68020 card for my MegaSTE. I intend to make version for STF (which should also work on Mega ST) and STE once this proto is done and tested. exxos allowed me to post the progress on his website (instead of doing it on mine as I wanted to keep this with the V2 booster we're working on as some of the CPLD code is common to the 2 projects). You can find the current status there : http://www.exxoshost.co.uk/atari/last/020BOOSTER/ I'll update this page as I make progress and will also do some quick status update here (mostly post about the issue I have and ask for help ). So far the card is assembled and I need to finish the CPLD code. Then the testing starts .... as well as the problems Regards, Rodolphe