Leewrigley

@Kitrinx Im using vivado i dont know about you, but how were you able to get over the T65 implementation in your verilog proect, i can simulate just fine but i cannot synthesise because of compex port types, i saw on xilinx website it could have something to do with negative structures ie (-1 downto 0) i didnt see anything like that in the code though. What would the complex port type even be, i wonder if it could be adapted?

@ehenciak You sound like someone who may be able to help me with my amature attempt all im looking for really is to get any kind of display out of it so i have somthing to show for my project project_2.rar

managed to get it simulating now, not sure if it will synthesise or anything though not tried yet, looks to be running which is good, i notice that not much gets written to the TIA registers at all, only position registers really so il need to look into that, maybe have polarity of read write or something flipped somewhere. BTW not sure if you would know or not but for the tia in the data book it says that write operations are done on the negedge of the clock, do you think this would make much difference?

Thanks for that, unfortunatly my verilog compiler doesnt know how to deal with the vhdl because it has complex port types apparently... always something!

hey @Kitrinx, sorry to ask a million questions but in your t65 instanciation you showed me before.. what is RD for data input and also what is pclk1 and cpu_halt_n for the enable signal, i never had those before? thanks

So, within my TIA module, have a straight divide by 3 clock output which goes into the CPU, do i need to change the phase at all? i saw from the schematics that it worked this way but i just though i could generate clocks in the top level module and use them where needed. btw my clocks arnt 100% accurate but should do for the sake of this project, i divide the 100Mhz clock by 27 to get 3.57142... and divide that by 3, i though that the input clock for cpu riot and tia would all be the same 1Mhz clock input but i just reveresed the phase for all these because i thought thats what i was meant to do

How do set up this clock then sorry, i just use basic clock dividers for everything. right now my cpu clock which is used for riot and tia also and the 3.58Mhz tia clock can be seen in the ss attatched, which clocks do i need to change? just to one going into cpu or 1Mhz clock going into all 3? CLK2 is cpu and CLK is tia (obviously)

Is that the exact CPU you were telling me to use also? so i could take the CPU from that project and use the same line just change the names on the wrapper side? btw you are a massive help thank you

okay im going to try combat then and shorten the address bus, no reason its just how iv looked at it from the start, il convert it from now especially for screenshots so you can more easily tell what is being excecuted. i have no experience with VHDL, but if it will work exactly the same dropped in i can replace the CPU core no problem, would my call from before work the same? how do you call a VHDL file within a verilog one?

wait, really, would that work? if so i will do that and try to run combat as surely that is easier than pitfall haha

right now pitfall is the game i am running, i should probably move over to a simple game like combat so would copy and pasting the hex twice in a row make that work properly or no? il attatch a few images, one is how im loading the game, how long do you think i should give for reset? the other image is the moment that it craps out, for some reason the cpu spits out an adress of xxx's and then shortly after does it a second time, this second time is when all data stops flowing also just want to say thank you to everyone for their help so far edit: i now notice my naming is horrible, A is the address bus, D above is data intot the 'ROM' Din below is just data going into cpu

@Kitrinx wow, i had changed these before but to no avail, but alas i have done it now and its a lot better, not perfect, but better... edit: it probbaly worked this time because i had fixed some other problem in the mean time iv attatched a ss of the simulation, at one point the data from the ROM does become 0 and stay that way, is that mayb efter everthing is written and the game is waiting for the reset button?

if anyone happens to be bored and wants to have a look at my horrible programming skills then here is my latest zip project_2.rar

its actually a 6502 core btw, here is the wrapper i wrote to convert it, maybe i mucked this up but seemed simple.. module MOS6507 ( A, Din, Dout, RE, CLK_s, RDY_s, RES_s); output [12:0] A; //Smaller address bus input [7:0] Din; //Data bus input output [7:0] Dout; //Data bus output output RE; //Read write output (s to distinguish the shell) input CLK_s; //Shell Clock input RDY_s; //Ready line input RES_s; //Reset line wire [15:0] cpuAB; wire R_W_s; cpu6502 cpu (.clk(CLK_s), .reset(RES_s), .addr(cpuAB), .data_in(Din), .data_out(Dout), .we(R_W_s), .irq(1'b1), .nmi(1'b1), .rdy(RDY_s)); assign A = cpuAB [12:0]; //Convert 16 lane address bus into 13 lanes assign RE = ~R_W_s; endmodule

so far i have tested pitfall, defender and combat (hex mirrored to fit the 4k area), pitfall originally was "working" a bit better than others as it was the only one that was getting data written intot the tia registers including vblank, whereas others wernt getting anything like that