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pasiu

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  1. Unfortunately I've never checked Rapidus with 8/16k cartridges, so it seems we missed it during sw development. I think the bios uses some memory locations at $8xxx, so I will try to work on this to correct it.
  2. Actually it was not China . Here is the version of Rescue of Fractalus I used to record the video: http://atarionline.pl/arch/R/Rescue%20on%20Fractalus%21/Rescue%20on%20Fractalus%21%20%281985%29%28Epyx%29%28US%29%5Ba%5D.xex
  3. I'm also curious, because I've never tested Rapidus with MIO.
  4. I'm not sure if this is a problem Jon. Pressing Reset key to enter the Ultimate setup clears the $d1ff register in Rapidus and makes the other registers invisible. The other thing is that I'm not able to replicate such behavior (cold reboots) in my testing machines. I checked two XE computers, each of them have U1MB and VBXE installed and Rapidus of course. Unfortunately, to make U1MB cooperate with Rapidus in these Atari machines I had to solder some short piece of wire (5cm/2inch long) between GND signal of U1MB and the Atari motherboard. The one of indicators that you have to do this mod is the resetting of U1MB RTC, and that is why I asked you to check is few posts above. Can you do such extra connection? Long wires of U1MB to Atari motherboard have quite high inductance and considering that Rapidus provides signals with much faster rise/fall times, we can get some signals ringing and false writes/reads at the end.
  5. Yes, this is what I have in mind speaknig about the U1MB design and the way of working... Rapidus is a PBI based device, so it has registers on $d1 page. However the access to those registers is possible after you write $01 to $d1ff. I have implemented full address decoding, so register under $d1ff adderss is sensitive only. I will review my code to confirm that,
  6. This is because you're operating in the Atari memory, not Fast RAM. Switch the RAM #0-#3 options to Fast reads, and then check CPU frequency in Ultimate Setup. Displayed frequency at 2.38MHz can tell you one thing, that some internal operations of 65816 cpu were executed during the read or write cycle to Atari memory. This is becuse you had a CPU waitstates option set to OFF. If you switch it to ON, then you should get 1.77MHz. Did you load anything to memory before you pressed the Reset key? Which settings did you have in Rapidus menu? The way of how U1MB works make a lot of trouble to Rapidus. I was struggling with it for a long time, finally adding some extra logic only to handle this upgrade.
  7. Great Jon. Please keep us informed if there are any problems (for example check the real time clock in the U1MB setup). I tested Rapidus in my 1200XL some time ago, but not in such configuration (VBXE and U1MB). I don't know why Lotharek didn't send it. Maybe there is some reason. Small tip: The pin to connect GND in this 3-pin conenctor is really an ON/OFF pin. If you leave it unconnected, then Rapidus won't load the core to fpga at a start-up. You can also connect this signal to S0 or S1 output of U1MB and control it through Ultimate setup. Unfortunately the logic is inverted, so Rapidus will load the core if you set the Device 2/3 option to "Disabled".
  8. Thanks Draco. I think I wouldn't explain these points better than you did. I will try to put some more information to user's guide. 65c816 clock frequency is constant - 20MHz and you can't change it. This is a major difference if you compare Rapidus to some older projects like Turbo816 or Warp. Rapidus in the way of working is very similar to HyperSpeed XL/XE project or SuperCPU for C64. As you can imagine 20MHz is too high for some devices attached to the adderss/data bus of 65c816. Flash memory is a good example, because it needs around 70ns for reading cycle. Full 20MHz cycle takes 50ns. The solution for that is introducing the waitstates for CPU to let it wait for data for more amout of time. It can be half of cycle (25ns), one cycle (50ns), 1.5 of cycle and so on. In case of 70ns flash memory I had to add 1 full cycle (in other words 1 waistate) to make it work. Practically the CPU PHI2 clock signal has low level state always 25ns, but logic 1 state time depends on how many waitstates is needed. Zero waitstates means 25ns of logic 1 state on PHI2 signal, but every extra 0.5 of waitstate keeps this logic 1 on PHI2 for the next 25ns. For Flash memory we need 1 waitstate, so full access cycle takes 100ns and the real CPU frequency in this case drops to 10MHz. More complicated is an access to Atari bus. For data exchange between Rapidus and Atari some extra logic was required. There is a data buffer and state machine which help in reading and writing data from/to Atari bus. If 65c816 needs some data from Atari memory or Atari registers, then MMU (in Rapidus) send the request to that state machine. This state machine stops the 65c816 (puts long and undefined waitstate), latches 65c816 address and starts the reading cycle on the Atari bus. When data is read, it is stored in data buffer. After that state machine provides it to 65c816 bus and resumes the PHI2 clock (removes the waitstate signal). The opposite way is similar. When 65c816 must write data to Atari bus, it stores this data to data buffer first and the MMU informs state machine to start writing cycle stopping the 65c816 until finished (or even not stopping in some conditions). After you change any option in Rapidus Menu you have to save it to eeprom memory pressing Esc and chosing Save and Exit. New settings are applied immediately and after every Reset. It may happen that the memory content (after change of working mode) will not allow to start the 65c816 properly. Sometimes reset helps here, but not always, so power off/on procedure may be required to clear RAM. Maybe Draco can say something more about this. If Rapidus started Missile Command, than it means that U1MB had connected this ROM to Atari bus. I see no other option here, becuase Rapidus doesn't modify any of U1MB registers. Don't you think it is not the most reliable method to test the speed? It is based on your observation, not real calculations. Please consider that the Basic ROM is in the Atari memory area, so every access to it is long. Very long. If you want to speed-up your Basic, than load it to RAM. Try Draco's U-BASIC (download available on his site). Do you mean 6502C made by Rockwell? Personally I haven't noted any issues with this version of 6502, but maybe I don't have the "bad" one. For testing purposes I have the Rockwell chips with production datacodes 8336 and 8719. Hair drayer is a good method to heat-up the chips inside the Atari, but from the other hand you're not controlling the temperature. Do you know what temperature reached the CPU and if you are not above the limit? Just one OS, but you can replace it for the other. There is a flashing tool available. Be aware that if you use OS without PBI device support, then you will not able to enter the Rapidus Menu using Reset+Inv keys. In this case you have to load small program from external disk to run the Menu. It is more for extra peripherals, not memory. But of course you can add more RAM if 30MB is not enough to you. Anyway, thanks Guus for good discussion.
  9. Hello Guus, thanks for your comments, but I'm not sure what are you expectations from having the turbo card in your Atari. If you are thinking that everything start to work faster, than I have to disappoint you. Old software, especially games, works without visible speed-up effect. That is because the Atari bus frequency doesn't change after you install Rapidus inside your computer and it still remains 1.76/1.79Mhz. Apart of that many games are synchronized to vblank interrupt, so increased CPU clock frequency doesn't do any change. Rapidus speed-ups the operations on the memory, but not by just simply replacing the Atari memory with Rapidus fast RAM. This approach will not work, because for example Antic still requires the screen data in the basic 64k area. To make it work I had to use some trick which is mapping of the 64k of Atari memory into fast ram (connected directly to 65816 bus in the Rapidus interface) and the proper management of reads from and writes to that area of the memory. There are some registers to set up the working mode in specific address areas, but to have it user friendly, we created a configuration menu which can be accessed by pressing the reset+inverse keys combination. Thanks for calling it "nice", but is the very useful tool if you want to work with Rapidus in optimal way. The menu offers you following options: Preference Here you can chose the predefined working mode of your machine. Changing this option you can select very fast between 6502 mode, Sweet16 mode or the most powerful Rapidus mode. RAM #0-#3 Here you can select the operation mode of the Atari memory. #0-#3 numbers tell you which 16kB area is impacted by this option: #0 - $0000-$3fff #1 - $4000-$7fff #2 - $8000-$bfff #3 - $c000-$ffff You have following available settings here: No Speed-up - in this mode 65c816 writes the data to Atari memory and in parallel to Rapidus Fast RAM, but all the reads are from Atari memory only. This option makes delays, because 65816 has to wait very long for data from Atari memory. Fast Reads - in this mode 65c816 writes the data to Atari memory and in parallel to Rapidus Fast RAM, but the reads are from Rapidus Fast RAM this time. This option removes delays in case of readings, because there are no waitstates created during access to Rapidus Fast RAM. Fast rd/wr - this option is available only in the first 16kB area (#0), the data is written to and read from the Rapidus Fast RAM only, so every operation is with 20MHz frequency. But you should be very careful using this setting, because the screen data must be outside this area, otherwise you see some garbage on your screen or just black screen. This mode was added to speed-up the zero-page and the stack operations. SDRAM 4k cache - this option speed-ups the SDRAM memory by introducing some additional cache memory. SDRAM begins from address $080000 (or $100000), so if you don't work in this memory area you will not see any difference. Primary CPU option selects between 65816 and 6502. If you select 6502, then 65816 is stopped just after it enables and resets the 6502. The only way to wake up the 65816 is to press Reset button. CPU waitstates Here you can enable the waitstates when 65816 does some internal operation (when both VPA and VDA signals are 0). This option must be ON when you want to simulate 1.76/1.79MHz operation speed of your 65816 in the first 64kB of memory area, otherwise it is better to set it to OFF, CPU addr. wrap When ON, then the zero-page area is mirrored into first bank of 65816 CPU ($010000-$0100ff). Additionally the 65816 must work in emulation mode. This option was added to solve one problem (or maybe it is a feature ) with 65816. If you load to X register $ff, then performing LDA $FFFF,X operation results, that CPU read the data from $0100fe, not $0000fe. Some programs without this option set to ON don't work properly, or don't work at all (examples - Qmeg 4.04 menu, Near or Reditus demos). System ROM - selects the ROM between the ROM from Atari motherboard or 65816 OS available in Rapidus Cartridge ROM If you want to connect any kind of cartridge which use $8000-$9fff or $a000-$bfff areas (including Atari Basic), then set this option to ON. This option was added to provide clear information to the user, but in reality it is a duplication of RAM #2 option. Cartridge ROM ON corresponds to No speed-up setting in #2 area. U1MB Expansion If you are the Ultimate 1MB user, than set this option to ON. We didn't find a way for U1MB autodetection, so this must be set manually. The Rapidus bios (the menu is a part of it) does more things. It detects the VBXE and the size of portB based expansion memory and after that sets appropriate registers. Without it Rapidus will not function properly accessing the 64kB memory space of the Atari. The bios also reads and writes the settings data to eeprom memory. It also controls old 6502 CPU. Anyway try to play these options to see the differences in programs behavior. Personally, as a SDX user, I have "Rapidus" mode selected (in Preference option) most of the time. There is significant speed-up and increased comfort of working. If you are still not sure if your Rapidus does work, then load and check Karateka game. I know it is not playable at 20MHz, but it will show you the capabilities of the Rapidus Accelerator. Try to run also Rescue of Fractalus game or Mercenary. If you are fan of this games, then you will like them even more. At the moment I have no plans to publish the schematic. Most of the logic is inside the cpld and fpga devices, so the schematic won't provide you many valuable information how Rapidus works. The memory map will be shared, but some of Rapidus registers will be marked as reserved. Regards, Michal
  10. It is not available yet. Adapter for 800XL is still in development. Well, F7 project is on hold and most probably it will be cancelled. I doubt if F7 would offer the same features like Rapidus, because F7 uses quite old technology devices. It will be hard to redesign this extension now. I think it is worth to try connecting Rapidus to Atari 800 equipped with Incognito board. Some adapter must be just designed for that purpose. Unfortunately I do not have the Incognito board and also I'd like to keep my only one 800 model in non modified condition... There is one important information which is missing in Lotharek's instruction. If you are user of any kind of PBI based device (IDE+, U1MB+Side and etc.) make sure it has PBI number set to other then 0. Rapidus uses this number and it cannot be changed, because it is hardcoded in cpld and fpga. Two PBI devices with same PBI number may result a Self Test on your screen.
  11. It is really great to see it working in your computer. It's quite stressful situation to me, as a HW designer, releasing such project to Atari Community. Maybe just one comment to the options in your settings menu. If you don't have the Ultimate 1MB extension installed in your machine. then set the "U1MB Expansion" to OFF, otherwise you can have some problems with running the system ROM from Rapidus. All the necessary information will be included in the Rapidus User's Guide, but unfortunately it is still not finished yet.
  12. Rapidus works in 800XL, but it needs extra adapter. Without it you won't be able to close the housing cover of your Atari. Here you can see Rapidus in action inside my 800XL. http://youtu.be/G4Bb0QBlIYI Mentioned adapter is not ready yet. Please be patient.
  13. There is an idea to add hdd controller, but as a second board connected to Rapidus. I even started the design many months ago, but Rapidus had higher priority. Here you can see picture of "Portus" on early stage of pcb design.
  14. New Device is the common name for peripheral devices connected through parallel interface (PBI - XL models) or CART/ECI (XE models). All computers starting from 600XL/800XL models with original operating system are able to work with New Devices, however some of XE models (65XE w/o ECI and XEGS) need an extra hardware modification. Old 400/800 and 1200XL computers have operating system without New Device handling routines, so they are not able to work with New Devices. These models require more modifications done in hardware including OS replacement, but installation of Incognito in 800 or Ultimate1MB in 1200XL should help here a lot.
  15. Ok., below I've tried to clarify some points. If you didn't find the answer on your question, please ask. NTSC-friendly? Rapidus adapts to the Atari bus frequency, so it does not matter if you have PAL, NTSC or even SECAM computer. Speed(s)? (e.g. 1.79, 7.16, 14.32, xxx) Software selectable? Fast mode at 20MHz and special access modes to first 64kB of memory. You cannot select clock speed, but you can set your access mode. Additionally you will keep still your standard 6502, so you can use it in case of any compatibility issues with old software. Currently you must switch off Rapidus when you boot you computer to use 6502, but maybe in a future both microprocessors will be able to operate in parallel (hardware supports that, but control software does not exist). How much standard fast ram? 512kB of SRAM and 32MB of SDRAM (30.5MB used). Is there Rambo (etc.) on-board or will it work with typical internal or PBI ram upgrades (Freezer ram)? PortB memory expansiom is supported and recommended. Every kind of ram upgrade hardware should work, but it is physically not feasible to test it in advance. Axlon upgrade is not supported, but may be added in the future (I don't own this kind of upgrade). Supports IDE+2 Yes. Supports VBXE? Yes, but currently you should inform Rapidus manually that you have VBXE. Later there will be an autodetection (I hope). Supports Ultimate 1 MB? Yes, I use it in my test computer. Like for VBXE you should inform Rapidus manually that you have it installed. Flashable or programmable to battery-backed Sram if changes are made? (or requires new CPLD?) New FPGA core can be easily reprogrammed from disk since it is located in a flash memory. To change CPLD you need JTAG compatible programmer, but now I do not see a need to do it. All critical functions are in FPGA. "Friendly" with dos other than SDX? Yes. I used to work also with DOS II+/D, but SDX gives you more advanced control. Works with MyIDE-II cart? Never checked. SIDE2 works in its two modes. Works with different OS? Rapidus requires OS with New Device support, becuase this is a primary method to load FPGA core from flash memory. Second method is loading core from the disk, but considering core size (unpacked takes more than 300kB) it's a quite long process. You can also flash some OS into Rapidus and work at full speed. Works with typical productivity carts (Basic XL, Action!, etc.) Never checked, because I don't have them. SDX is in fact cartrige, so other carts should work as well. Probably I'll be able to test Atarimax Maxflash soon. Does this work with the "Adaptus board"... and what does the "Adaptus board" look like? Adaptus board is a Atari bus buffer device. It should not be required now, but if you have many many strange upgrades in you machine, than it may be needed. Adaptus is still in development. Does it accidentally work in an 1200XL too? Well...yes, but newer OS with New Device support is recommended in this case. You should also provide Extsel and MPD signals to Rapidus which are normally not available in 1200XL. If you don't want to upgrade your 1200XL, than you will have to load fpga core each time from a disk (it is time consuming).
  16. Not yet. First of all I have to test newer revision of Rapidus and then we will see. Right now I'm waiting for the delivery of new PCBs (ordered 2 days ago), then soldering and trying to run it. I hope to know everithing whithin 1-2 months.
  17. Please be patient. There are lots of things to be done, before releasing the projects to any kind of production. I'm more focused on Rapidus Accelerator than F7 now. It gives you more features and overall flexibility. I'm planning to make a one more revision of prototype with some improvments. There is an idea to speed up it a little bit, but I need to test it having a new PCB. Reworking of the existing design may be too difficult. The only version of VBXE which have been ever tested is 1.1. I have never observed the issues in the compatibility. Newer designs 2.x need to be chcecked (my 2.1 still waiting for installation), but I do not expect the problems here as well. TXG: Rapidus and F7 cannot work in parallel if think about it. Should be possible to have them in one machine, but just one can operate in the same time.
  18. Yes, if your 1200XL has XL OS and MPD and ExtSel signals are available, Rapidus should work. VBXE is fine. In one of my testing machines I have VBXE 1.0 and have no problems. The stability issues may be observed if you have many HW expansions, where data and address lines are overloaded. Special adapter with signal buffering should help in this case.
  19. Hello Everyone Well, I was not sure, if I should publish any data related to this project or wait few months more. I'm not used to show anything before it is really worth of that, but I decided to give you some details. As you already know Rapidus Accelerator is the turbo card for Atari 8-bit machines. It is designed to be used in models with New Device feature support, so unmodified 400/800 and probably 1200XL won't work as it was intended, however, I'm not saying that it is not possible to use it with 400/800/1200XL machines. It has been never tested. Installation inside the computer is quite simple. You have to put Rapidus board in place of removed 6502 and this 6502 you have to insert into socket on Rapidus card. Than you have to connect just 3 wires... or not, if you want to load the fpga core from external device. Compared with, for example VBXE, Rapidus doesn't have any additional microcontroller to load the core. This task belongs to 6502. Of course every atari model has its own mechanical constrains, so in case of need additional adapter should be used then (with or without additional signal buffering). Design of adapters is in progress. Rapidus is a quite complex device, because replacing only the old 6502 with new 65c816 won't allow you to increase the clock speed, use linear memory above the 64KB or do any usage of ABORT interrupt. You get wider instruction set and that's all. The idea implemented in Rapidus was to separate fast 65c816 bus from relatively slow atari bus and use so called data bridge to exchange the information between those two "creatures". This is not easy, because the data bridge has to emulate all timings as original 6502 CPU has and control 65c816. The thing is complicating more, if we consider, that atari bus is controlled also by Antic. This is a main reason why to have cpld/fpga on the board. The next good reason is flexibility. FPGA can give you more features, than just few input/output registers. Clock multipliers, additional ram and rom without any additional waitstates generation and more. We should also remember, that new logic devices are not 5V tolerant, so voltage translators are more then welcome. So, at the end we get: - 65C816 CPU operating at 16MHz completely asynchronously to Atari bus, VCC at 5V (unlike the rev.1b where ~14MHz clock is used and 3.3V), - 512kb or 1MB of zero waitstate SRAM, - up to around 30.5MB of storage ram - SDRAM clocked 128MHz (14.5MB and 113MHz for rev.1b), - 512kB of Flash memory (256kB is reserved for fpga cores, 256kB for OS and New Device handler) - 256b of I2C EEPROM for settings (rev.1c only) - and more features implemented inside the fpga, but I don't want to describe them now. Regarding the connector. It is something like parallel bus and it's going to be used by daughter board called "Portus". Project is not ready to be released. There are some things to be done in hardware, but more critical is software. A lot of code must be written first.
  20. I think that there is no need to keep the equation files as a top secret anymore. Feel free to modify whatever you want. U1 device: ;PALASM Design Description ;---------------------------------- Declaration Segment ------------ TITLE IDEaBios PATTERN REVISION 2.0 AUTHOR Michal Pasiecznik/Pasiu COMPANY DATE 10/05/05 CHIP _ideabios PALCE16V8 ;---------------------------------- PIN Declarations --------------- PIN 1 RW COMBINATORIAL ; PIN 2 A8 COMBINATORIAL ; PIN 3 A9 COMBINATORIAL ; PIN 4 A10 COMBINATORIAL ; PIN 5 A11 COMBINATORIAL ; PIN 6 A12 COMBINATORIAL ; PIN 7 A13 COMBINATORIAL ; PIN 8 A14 COMBINATORIAL ; PIN 9 A15 COMBINATORIAL ; PIN 11 O2 COMBINATORIAL ; PIN 12 EXTSEL COMBINATORIAL ; PIN 13 MPD COMBINATORIAL ; PIN 14 DIR COMBINATORIAL ; PIN 15 WE COMBINATORIAL ; PIN 16 GATE COMBINATORIAL ; PIN 17 OEROM COMBINATORIAL ; PIN 18 OERAM COMBINATORIAL ; PIN 19 D1XX COMBINATORIAL ; ;----------------------------------- Boolean Equation Segment ------ EQUATIONS /D1XX = A8 * /A9 * /A10 * /A11 * A12 * /A13 * A14 * A15 /GATE = A8 * /A9 * /A10 * /A11 * A12 * /A13 * A14 * A15 * O2 * /MPD /DIR = RW * /MPD /OERAM = RW * O2 * A9 * A10 * A11 * A12 * /A13 * A14 * A15 /WE = /RW * O2 * A9 * A10 * A11 * A12 * /A13 * A14 * A15 /OEROM = /A9 * A11 * A12 * /A13 * A14 * A15 + /A10 * A11 * A12 * /A13 * A14 * A15 /EXTSEL = A11 * A12 * /A13 * A14 * A15 * /MPD ;----------------------------------- Simulation Segment ------------ SIMULATION ;------------------------------------------------------------------- U2 device ;PALASM Design Description ;---------------------------------- Declaration Segment ------------ TITLE IDEaReg PATTERN REVISION 2.0 AUTHOR Michal Pasiecznik/Pasiu COMPANY DATE 10/10/05 CHIP _IDEAREG PALCE16V8 ;---------------------------------- PIN Declarations --------------- PIN 1 O2 COMBINATORIAL ; PIN 2 RW COMBINATORIAL ; PIN 3 D1XX COMBINATORIAL ; PIN 4 A6 COMBINATORIAL ; PIN 5 A5 COMBINATORIAL ; PIN 6 A4 COMBINATORIAL ; PIN 7 A3 COMBINATORIAL ; PIN 8 MPD COMBINATORIAL ; PIN 9 A7 COMBINATORIAL ; PIN 11 OFF COMBINATORIAL ; PIN 12 CS1 COMBINATORIAL ; PIN 13 CS0 COMBINATORIAL ; PIN 14 D1FF COMBINATORIAL ; PIN 15 OH16 COMBINATORIAL ; PIN 16 WH16 COMBINATORIAL ; PIN 17 BANK COMBINATORIAL ; PIN 18 WL16 COMBINATORIAL ; PIN 19 IOW COMBINATORIAL ; ;----------------------------------- Boolean Equation Segment ------ EQUATIONS /IOW = A4 * /A5 * /A6 * /A7 * /RW * /D1XX * O2 * /MPD WH16 = A4 * /A5 * /A6 * /A7 * RW * /D1XX * O2 * /MPD /OH16 = /A4 * /A5 * /A6 * /A7 * RW * /D1XX * O2 * /MPD WL16 = /A4 * /A5 * /A6 * /A7 * /RW * /D1XX * O2 * /MPD /CS0 = /A3 * A4 * /A5 * /A6 * /A7 * /D1XX * /MPD /CS1 = A3 * A4 * /A5 * /A6 * /A7 * /D1XX * /MPD /D1FF = OFF * A4 * A5 * A6 * A7 * /D1XX * O2 * /RW BANK = A5 * /A6 * A7 * /D1XX * /MPD + /A5 * A6 * A7 * /D1XX * /MPD ;----------------------------------- Simulation Segment ------------ SIMULATION ;------------------------------------------------------------------- Michal pasiu/ssg
  21. pasiu

    Rapidus 1c

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