When I run this code on 8bitworkshop my sip is toward the left side of the screen (which is what i want), but when i run the code on z26 emulator it's still facing toward the right of the screen.
processor 6502
include "vcs.h"
include "macro.h"
;variables
seg.u Variables
org $80
YPosFromBot = $80;
VisiblePlayerLine = $81;
PlayerBuffer = $82 ;setup an extra variable
seg Code
org $F000
;generic start up stuff...
Start:
CLEAN_START
ClearMem
sta 20,x
dex
bne ClearMem
lda #$00
sta COLUBK ;start with black background
lda #$08
sta COLUP0
;Setting some variables...
lda #80
sta YPosFromBot ;Initial Y Position
lda #$20
sta NUSIZ0 ;Quad Width
;VSYNC time
MainLoop:
lda #2
sta VSYNC
sta WSYNC
sta WSYNC
sta WSYNC
lda #43
sta TIM64T
lda #0
sta VSYNC
Movement:
lda #%00010000 ;Down?
bit SWCHA
bne SkipMoveDown
inc YPosFromBot
SkipMoveDown
lda #%00100000 ;Up?
bit SWCHA
bne SkipMoveUp
dec YPosFromBot
SkipMoveUp
WaitForVblankEnd:
lda INTIM
bne WaitForVblankEnd
ldy #191
sta WSYNC
sta VBLANK
ScanLoop:
sta WSYNC
lda PlayerBuffer ;buffer was set during last scanline
sta GRP0 ;put it as graphics now
CheckActivatePlayer
CPY YPosFromBot
bne SkipActivatePlayer
lda #8
sta VisiblePlayerLine
SkipActivatePlayer
lda #0
sta PlayerBuffer ;set buffer, not GRP0
ldx VisiblePlayerLine ;check the visible player line...
BEQ FinishPlayer ;skip the drawing if its zero...
IsPlayerOn
lda Ship-1,x ;otherwise, load the correct line from Ship
sta PlayerBuffer ;put that line as player graphic for the next line
dec VisiblePlayerLine ;and decrement the line count
FinishPlayer
dey
bne ScanLoop
lda #2
sta WSYNC
sta VBLANK
ldx #30
OverScanWait:
sta WSYNC
dex
bne OverScanWait
jmp MainLoop
Ship:
.byte #%00000000
.byte #%00100000
.byte #%01111000
.byte #%11111100
.byte #%01111111
.byte #%11111100
.byte #%01111000
.byte #%00100000
org $FFFC
.word Start
.word Start