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About DeadlyKitten36

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    Combat Commando
  1. Hey, just wanted to make a final post here thanking everyone for the help again and giving a quick update I'm probably going to come back to this at a later point when I've learned a little more about emulation and programming in general as I've been feel more and more out of my depth working on this. If anyone is interested, I put up what I had so far on GitHub. https://github.com/nd3644/e6502-vcs It got as far running most of the examples from 8bitworkshop and partially runs a few official games but there are timing issues and some things missing in the TIA. Again thank you for the advice, I hope to come back to this at a later point
  2. Hey, Just wanted to drop a message and say thank you again, this information was super helpful- Just trying to find some time to work on this stuff So far I found I wasn't handling 73 cycle WSYNCs correctly, there were some page crosses I forgot to include also. I will write back and let you guys know if I make progress
  3. Thank you both for the replies! I have a basic debugger in and I've been stepping through ROMs side by side with stella. I think part of my misunderstanding comes from the beginning of ROMs where intialization happens (CLEAN_START etc).. I think some problems could derive from the mirrored addresses (WSYNC being both 02 and 43 for example). To try and find exactly where I fall out of sync with Stella I added a "frame count" & "cycle count" but I'm having problems with even that. For example, here is the ROM for donkey kong, and I noticed Stella moves to "frame 2", on "scanline 50" the final BPL. Maybe someone here can help me understand this? 😕
  4. Hey, I wanted to ask if anyone could help me with understanding WSYNC and other potential timing curveballs I implemented timing as dirtyhairy described, most ROMs I've tested work almost perfectly but I'm running into a lot of cases of being off by one CPU cycle quite a lot. I guess I wanted to ask if anyone knows of any curve balls I should be considering? One thing I tested (and this could be false) is performing a WSYNC puts the beam at 6 CLK even when strobed with longer instructions (sta WSYNC,X) etc I'll keep going over the code and testing with Stella but if anyone had any advice on what I should review Also, for anyone who worked with a lot of 6502, does page crosses play into the timings a lot in time dependent sections of the code? Again, I really appreciate the help. Really enjoying my journey learning about this console !
  5. Holy wow that's quite a goldmine haha. Thank you so much <3
  6. Thank you for the response DirtyHairy, I appreciate it! I did some reshuffling and I seem to be getting the desired output by moving the effects of each opcode to the last cycle. I'll keep on studying and report back if all goes well ^_^ ~
  7. Hey, Sorry to ressurect and old thread I've made a lot of progress on this project and I was hoping someone might be able to lend me some advice about managing the timings of the CPU / TIA a little as it's been difficult to get this right My approach has just been to associate a CPU count with each opcode and then advance the TIA CLK 3x the length of the opcode. The execution looks like Check_Opcode() PerformLogic() AdvanceCLK(3 * LengthOfOpcode) ... I was wondering... Is this naive? Do some ROMs rely on the 2 clocks in a STA before the storage actually completes in a graphics register? It seems like every time I make a change to this timing some other binary starts misbehaving and I wonder if I'm fundamentally going about this incorrectly. Thank you for reading <3
  8. Thank you everyone I i really appreciate you taking the time to help out. I think I understand how these registers are supposed to work better- Now to try implementing it
  9. Hey, Over the last few weeks I've been working on a 2600 emulator as a hobby project and I've had some issues understanding how certain things works. In particular learning assembly and the 6502 is very challenging but I was wondering if anyone would be kind to help me in learning about the 2600 itself. I'm currently trying to figure out how I would emulate the TIA, and my most recent issue relates to the way you use HMOVE/HMP0 registers to achieve smooth scrolling. From what I understand, you use HMP0 as a relative offset to shift the pixels of the sprite to adjust for the 3-1 ratio of CPU - TIA clocks. I found a TIA document online saying that you use the latter 4 bits of HMP0 to determine the offset from -7, + 8. But what I don't understand is why you would need this kind of range when you only need to move the offset 3 pixels at a time. I hope this was coherent, any advice is really appreciated.
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