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its-a-feature

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Posts posted by its-a-feature


  1. So I've been trying to figure out how to draw sprite in 6502... my main problem is that either it doesn't show the sprite at all, or if I'm trying to follow a tutorial it doesn't work since it's NTSC and I'm using PAL.

    I'm really confused as to how it works so if anyone could shed some light on it, that would be much appreciated.


  2. 10 minutes ago, NoLand said:

    Mind that you'll have to (a) write the first value/pattern of PF0 on the start of each scanline for the left side, then wait for PF0 having been actually displayed and then set the new value – and this for each line. Start counting your cycles at WSYNC.

     

    E.g.,

     

    sta WSYNC ;strobe WSYNC to be woke up at start of next scanline
    
    lda #%00010000 ;[3 cycles]
    sta PF0        ;[3 cycles, now at 6]
    
    lda #%01110000 ;[3 cycles, now at 9]
    sta PF1        ;[3 cycles, now at 12]
    
    lda #%11111100 ;[3 cycles, now at 15]
    sta PF2        ;[3 cycles, now at 18]
    
    lda #00010000  ;[3 cycles, now at 21] load right-side PF0
    
    ;now wait until PF0 has been displayed
    ;scanline display starts at the end of cycle 23
    ;+ 4 fat pixels = 4 * 4 / 3 (pixels per CPU cycle) = 5.333
    ;so we'll have to wait at least until cycle #28 has passed.
    ;on the other hand, we should be done before cycle #49,
    ;when PF0 is used by the TIA again for the right side.
    
    nop ;[2 cycles, now at 23]
    nop ;[2 cycles, now at 25]
    nop ;[2 cycles, now at 27]
    
    ;mind that the value will be actually set only at the end of
    ;the last cycle of the STA instruction, so we're good to go
    
    sta PF0 ;[3 cycles, now at 30]
    
    ; now wait for PF1 (compare the chart)
    ; and for PF2 ...

     

    That makes sense, and it works now... thank you!


  3. 30 minutes ago, Karl G said:

    In a nutshell, you need to count cycles for your scanlines, and write to the registers at the right time.  For the left half of the playfield, you write to the playfield registers before they are displayed on the screen.  For the right half of the screen, you write to each of these registers again after the left portion of that playfield register has finished displaying, and before the right half has begun displaying. This timing chart is invaluable for determining when to perform these playfield register writes.

     

    For example, for PF0, for the left half of the playfield, you will want to complete the first write to this register by cycle 22.  For the second write, you will want to complete the write between cycle 28 (when the left half of PF0 has been drawn) and cycle 49 (when the right half of PF0 starts to display).

     

    TIA-timing.thumb.png.0a17460dd4a1411b1d16cba679b3919d.png

    Okay I tried to take that and implement it, but it's still not working... Is there something I'm missing?

    Here's my code...

    Kernel
     ldx #242
     lda #$55
     sta COLUPF
    
    LOOP
     cpx #49
     bcs SKIP
     
     lda #%00100000
     sta PF0
    
    SKIP
     sta WSYNC
    
     dex
     bne LOOP
     rts

     

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