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About Windless

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    Space Invader
  1. Yes, I did. If you want me o try getting it from the crystal or test something else, jut ask. Thank you for all the help you provide Windless.
  2. Ok, sorry I haven't been clear let me try to fix that : -I first measured with a disconnected 2600 between TIA 3.54The MHz clock input and the clock input of the 74LS174 so i thought they my be connected though a resistor or something. Then I tryed to follow the track from the 74LS174 clock pin,and found it reached the NAND gate -the weak clock signal,yellow in the fist two picture of my previous message,is the TIA clock pin -the clean (but a bit overshooting) clock in the last picture is taken at the clock pin of 74ls174 and comes from the output of the NAND gate. I didn't follow the entry of this gate but since the output is same frequency and inverted when compared to the TIA clock, I guess that is where is comes from. That's what I expected to find, but manually digging through the first 50.000 points I recorded, I didn't see that happen.
  3. the NAND gate is used to generate a clock signal that is the inverse of the TIA clock : if we look at how the LUM signal rises after the TIA clock,we see it is not completely ready when the clock rises : With respect to the inverted clock from the NAND gate, on the other hand, it is more reliable : Ok, so I have a clan LUM signal I can use, but it is half a (TIA) clock delayed compared to COL and SYNC.
  4. I've found he datasheet of the SGS T74L1741B,the exact same one that is on my 2600 here. In the meantime, I also stopped confusing D-flipflops and T-flipflops, and now can tell : the T74LS174B1 has the same role as the CD4050 : it buffers the LUMx signals (only LUM on the SECAM) in addition, it is clocked with a 280ns (this is the 3.54...MHz used by the TIA but it does not share the track with it : the signals comes from a SN74LS00N quadrulple NAND gate - maybe the TIA also gets its clock from there but with a DMM I find a 2kR resistance between T74LS174B1 clock and TIA clock - maybe the clock is delayed to wait for the TIA to output on its LUM pin before the flipflop clocks it ?) !MR (reset) of the T74LS174B1 doesn't seem to be used. So I apparently could take the LUM signals from the hex flipflop.
  5. ok, apparently the T74LS174B1 is not a T74LS174. It seems to be just a buffer like the 4050 : the T74LS174 as a !MR (master reset ?) but the datasheet says it set output to 0 whatever Qx is, so maybe they are just different components ? I have a 2x12Mpts record (12MB once compressed) if someone wants to have a look.
  6. The PAL version of the field manual gives some answer : The cheapest 8MHz crystal on mouser has a 25ppm precision, we can hope the crystal on bluepills is not more than 400 times that, so +-0.04MHz s really possible Now the 4.43MHz clock will have to be derived from the 72MHz bluepill. The period of the PWM signal generated by the timer can be adjusted with a one cycle precision. We need 6.5% precision and we have 1/72.000.000 precision Conclusion : precision is not an issue. Output level might be if the clock signal should not oscillate between 0 and 3.3V, but if there is a bluepill anyway, adapting the outputwill still be easyer / cheaper than making a complete clock. Synch with the 900kHz signal from PAL-S can still be an issue thought.
  7. Some guy sells 2 dead motherboard for 15€ in france, but he is on the other side of France and do no want to ship them to me
  8. Ok, there is definitively something I don't understand : if the part that are connected to pin 7 of the DB9 port and stady +5V, and pin 8 stay at GND, then I see no way out for the audio signal : Is the schematic missing some connection, maybe from the left part of R210 to the RF module ?
  9. It needs to be tested, but I hope that : -PAL-I can be generated by the timer, -PAL-S can be put on an interruptable pin, and hopefully since it need to trigger at 900KHz (15 times per VBL) it happens during VBLANK so it won't slow the colour conversion -Reading the 3 LUM could be just one cycle -Reading COL would require reading a timer when a signal occures -Then combining everything and reading a lookup table could take a few cycles -Generating the SYNC can be done while waiting for COL or while outputing RGB values ? I did not write the code, but it's probably 10-20 cycles total. Since the TIA is 3.54MHz on pal when the bluepill is 72MHz, that *may* work. But it only work if the 1.55% error additionned to the error of the blupill crystal is precise enough for PAL-I It has a few 5V tolerant pins, IIRC scart is 0.7V so output will be ok also. Disclaimer : I have very few experience with microcontrollers, and none with analog signals, I may forget lot of things.
  10. Do you have a schematic of this part ? Because from what I could see, the LUMx output of the TIA seems to be directly connected to the inputs of the D flip-flops. Maybe the three other inputs/outputs of the hex fliflop serves this purpose ? (the tracks run under some IC, I will ty to find a cheap broken 2600 to remove components and make a complete schematic) Ho, so maybe I made some wrong assumption and the sound goes to J201.11 and is muliplexed elsewhere ? (by an mc1373 like on my SECAM 2600, even thought its datasheet says it expects color on the same pin as sound, but probably it does not hurt if color is already multiplexed with ULM and SYNCH ?) Is it open source ? Because if I'm going to make a PCB for the clock anyway, It would be nice to make an all-in-one one. I also, I still have not given up the idea of using a $2 cortex board, which could generate the clock and scan the output from COL, and generate RGB to a SCART. Not sure all this would fit on the 72MHz board, but it would be nice.
  11. On my board, instead of a CD4050, there is a T74LS174B1. Apparently it would be a flip-flop (the datasheet if for t74ls174 no b1), it buffers AND keep he value until next clock signal. An interesting thing is there is no pull-ups before the T74LS174. Are they required only because of the CD5040 ? Are they unneeded when you use some kind of buffer ?
  12. Ok. I'll wait to receive the DIP40 sockets (I don't want to bend or cut pins) to make the test on the PAL-U pin from the 3.5MHz signal. In the meantime, I can start trying to understand the other side of the schematic : This is the schematic of the PAL 2600 as found on atariage. I took this one because I have a PAL TIA on my REV7 SECAM 2600 board. The greyed part are the parts that I think are not relevant to the PAL signal generation. The untouched part are the one I am unsure about The red part is the 4.43MHz signal needed to generate PAL color. this is the one we already discussed. The blue parts seems to be a used to generate a constant adjustable voltage on DEL (CADJ) to adjust color. This is true if 1nF C203 capacitor is just here to clean the OSC signal and has no effect on the blue part, which seems true (but I'm not skilled with electronics). The green part is the part that needs be remade to generate the composite signal (without sound) Blue part Not much to say about this, except that on my board if there are potentiometer to adjust the delay, they are from the TIA (bottom right corner) and have been locked with some welding. The voltage at DEL seems to be a fixed 5.04V. Hopefully this dos not need to be changed. Green part -This seems easy to re-do. CD4050BDR seems to be still available at mouser. But is it the same pat ? The datasheet says it is an hex non-inverter buffer, the FAQ on this forum says it is a video buffer. -The output goes to J12. I guess this is the composite entry for the RF module,but the RF module on my PAL REV7 is quite different : it uses a MC1373 which has a separate Composite (lum + synch) and Color (+audio) input. Does it mean that if I want to reuse the HF output, I need to no connect R222 and R234 and input the two separated tracks into the MC1373 ? Or maybe I could just add a CD4050 an AV output as described by alex_79 here. Can I do that without disconnecting the existing part of the schematic to preserve the hugly HF SECAM output ? -I do not understand the part that is let B&W on the bottom right of the schematic. I guess J201/10 in ground (since it is connected to CD4050 pin 8, Vss), but then all the part with coil and the 2N3563 would be a can of modulated powersupply that would create a carrier, modulate it with AUD, and use this modulated output as a Vcc for the 4050, hence modulating the output to add sound on it ? Anyway with AV output, I can just ignore everything that is inside the purple polygon, add a CD4050 with a clean 0/5V on the its Vss/Vcc ? Or do I need to disconnect the existing components ? MC1373.pdf
  13. Cortex was a rather simple solution for me, but wht you propose is even simpler Wil try this. Thaks you, Windless. * : (I have two blue pill that I paid $3 a pair and don't use, would need to order the crystal, capacitors, and a coil of undefined value to reproduce the clock found on the schematic of the pal 2600)
  14. Do you think I can use a 22pf on the output of PAL-S to filter, read it with a blue pill (72MHz Cortex 0 board you can buy for $1.5), then generate a 4.43MHz-ish square signal to PAL-I with the Cortex ? This would introduce a delay of about 3 cycles (<50ns) to detect the crossing of the 890KHz signal, then I could generate a 16 cycles signal to PAL-I (4.5 instead of 4.43MHz). This is a 1.6% variation, which needs to be added to the variation of the crystal on the cheapo cortex M0 board. Could this be used to test to see if a signal appear on COL, even if the output is not good enough to get real secam colors ? Random guess : could the PAL-I signal be used only to modulate the output of COL signal, hence I could just tie PAL-I to +5V and get a square signal instead of 4.43MHz signal on COL ? I need to find some documentation about how subcarriers work
  15. Ok, the track fom pin8 of the tia (PAL-I) quickly reaches pin 2 on the 6507 (Vss). I tryed to understand from the schematic of the TIA if this should give no signal on COL or a signal that would not have the expected shape/timing on the NTSC / SECAM ouput but that's a bit complicated for me. I order DIP40 sockets so I can lift pins without too much deterioration of the IC.
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