Dr Pinball

Just started working on a cartridge emulator for 2600 using the Pico, code here: https://github.com/sigmafx/atari_pico Uses PIO to sample the address lines, interrupt to get the ROM data and PIO again to set the data bus. For a 2K rom Pico was happy to run at stock 125MHz, but for a 4K rom I needed to overclock to 250MHz, not sure why, maybe memory access is too slow across the larger rom size?? I'm not going to finish this to a complete cart emulator, I just want to be able to quickly transfer roms to see the results of development work, so send rom over serial link and start execution. I'll put together a cart pcb with address line buffering for 5v to 3.3v - data lines work fine at 3.3v.

I had this same problem. I checked continuity between the points on the edge connector and found a short. After examining the soldered connections and re-flowing I could find no issue. So I checked the pins on the stm32 and found a short between 2 pins. I applied a bit of flux and re-flowed around the area which fixed the short. Card booted fine.

Hi Like everyone else, wanted to say thanks for creating and supporting this fantastic project. I purchased the components separately from various sources but have found that chip prices / availability are starting to have an effect - STM boards are around $15 now. My question is that when playing an original game over RF (not composite modded) the image quality is poor, but when playing over the pluscart the image quality is superb - so good in fact that I won't be doing the composite mod - it is really that good. I wondered what the difference is? Maybe the pluscart uses less current than an original cart so puts less stress on the voltage regulator and capacitors? I haven't recapped the console yet. Has anyone else seen this and knows why there is such a difference? Thanks again David. P.S. I ordered an STM32 board from Kmust Store on Aliexpress and they sent me 2 X plastic rotary knobs worth about $0.00001 each!

Hi I am writing my first code for the 2600 and read about the clock delays associated with certain writes to the TIA. I was wondering how the TIA handles the following situation: TIA runs at a clock speed 3X the 6507 - so for every 3 clocks the TIA acts on, 6507 executes once The 6507 performs a write to a TIA register - the address / chip enable / data lines are set by the 6507 The TIA will then execute 3X before the 6507 executes again Does this mean that the TIA will perform the same register write 3X and hence delay the action of the register write? The address / chip enable / data lines won't change over the 3X clock cycles as they are asserted by the CPU, so I'm thinking the TIA sees the same input on its pins for 3 clock cycles and hence does the same write for 3 clock cycles? So as an example, if I performed a RESBL would that actually only ever work to a 3 pixel granularity because the TIA would see the RESBL for 3 clock cycles?