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I had a thought, are you loading the xex programs from dos?

I committed the missing lvds files now. These being missing is normal though, I should probably clean that up... cp: cannot stat 'iox_gluev4.vhdl': No such file or directory cp: cannot stat 'pokeymaxv4.vhd': No such file or directory I also soldered a new FPGA. Similar results on this with some shorted keyboard lines. I think in both cases its because I made a mistake when cleaning the board prior to soldering it on with some braid. I dragged the braid slightly which took off some solder mask. It didn't look too bad on the microscope but I guess it is enough for these shorts to happen each time since there isn't much clearance between the solder balls! So I will start again on another new board next week. I bought one of these to try reballing these few chips, I now have 3 chips to reball so think this is worth learning how to do: https://www.aliexpress.com/item/1005005959551085.html I'll order some new FPGAs from digikey to try out the other boards so I can remove the reballing skill variable though! In the meantime I think this is soldered enough to proceed with a few further tests. e.g. I can solder the audio output components and at least play some audio with it.

Think I forgot to commit those lvds ip

I was away for a few days. Good news: sio works break works! Bad news: Think my bga soldering was not quite good. So one keyboard line was stuck low. This was also the cause of sio not working. Anyway I took off the chip and cleaned it up. I’ll put another one on and add that chip to my ‘to reball’ pile (not tried yet but looks doable!)

Do you mean on the right or vertical clearance? I’ve moved the headers inside the board now so if it’s space to the right rather than vertical that will work.

Speed category 8 is fine (7 will also work but costs more) SC is the variant I use. SA will probably work but I didn’t try it. Since I am using SC I do not use the ADC. See page 5/6 of this document for these details: https://www.mouser.com/datasheet/2/612/m10_overview-2401081.pdf I think M153 + 4 layer could be narrower, maybe. A different option is keeping this fpga, going to 4 layer and putting the resistors in the bottom. Do you have another case where the footprint is an issue or are you thinking of the NUC?

I’m not adding any features, I think we have plenty and the software needs to catch up. In terms of what fits, it depends on the fpga size. To me there are three options: i) 10M02: For people who just want a vanilla mono or stereo pokey replacement and minimal cost. ii) 10M08: Fits everything if we only include dual pokey. iii) 10M16: Fits everything with space for more. U1MB software control works on all of them (v1 to v4) with the plugin. SPDIF requires the external oscillator fitting. I suggest putting this on all of them because it’s cheap enough, though it’s up to whoever builds them.

I think you can probably get away with almost any capacitor of approximately the right capacitance. Probably there is an optimum type/diametric with the best properties but I’d challenge anyway to tell me which is which with a blind test.

Changes in v4 (dug out from other thread): i) Somewhat thinner (headers move inwards) ii) 2 layer single sided while having v3 like features iii) Digital ADC iv) No io expander, so keyboard timing can be perfect v) No LM339s needed (uses the fpga lvds) ie small form factor changes, cost reduction, keyboard compatibility improvement and digital system audio mixing u1mb has a plugin. I do have a spare io pin that I could dedicate to switch back to mono mode for those who don’t want to use it.

The parts get quite a lot cheaper in volume at DigiKey so if anyone is able to make 50+ and ship them that’d be best! I don’t want to get into shipping more than 5-10 I’m afraid. I was wondering about the Abbic shop… Did you import the version with larger drill that allows for super cheap pcbs? Actually that is only a problem with low quantity, at 100+ small drills are ok.

I’ll answer this one in the coming days, looks you are almost there and I just didn’t automatically build some tools etc. @Mathy I see I just confused you with my reply, happy to explain more but perhaps you could ask again what isn’t clear?

Version Sub-version Analog audio outputs Audio output method Audio output coupling caps Digital audio output (spdif) Keyboard method Paddle method Audio input Spare IO Board Changes Issues 1 Compo 4 Sigma delta + rc (3.3v) FALSE FALSE io expander lm339 comparator 1 2 side, 2 layer, regulator sticks out, pin header on right Very quiet, paddles incorrect, keyboard issue with tkii 1 Final 4 Sigma delta + rc (3.3v) FALSE FALSE io expander lm339 comparator 1 2 side, 2 layer, regulator sticks out, pin header on right Make louder (rc values), fixed paddles(remove parts) Still fairly quiet, not enough io, keyboard issue with tkii 2 4 Sigma delta + rc (5v via buffer) FALSE FALSE io expander lm339 comparator 3 2 side, 2 layer, close to pokey size, pin header on right Added io, buffer chip for output, smaller Could still use more spare io, keyboard issue with tkii 2 b 4 Sigma delta + rc (5v via buffer) TRUE FALSE io expander lm339 comparator 3 2 side, 2 layer, close to pokey size, pin header on right Added ac coupling caps Could still use more spare io, keyboard issue with tkii 3 4 Sigma delta + rc + op-amp scaled TRUE TRUE io expander lm339 comparator Analog mixing via op-amp 11 2 side, 4 layer, close to pokey size, pin header on right. Parts on both sides! Op-amp audio output, analog mixing, lots of io Expensive to produce, keyboard issue with tkii 4 3 Sigma delta + rc + op-amp scaled TRUE TRUE FPGA direct FPGA LVDS build-in comparators Digital mixing 10 2 side, 2 layer, close to pokey size, inland headers Remove io expander, small smaller and cheaper pokeymax_features matrix.xlsx

Well the pokeymax project, as entered to abbuc, was intended to provide a low cost simple pokey replacement that supports all features in close to the original chip footprint. Nowadays there is more spare IO exposed from the FPGA allowing various modules to be enabled at core synthesis time, mostly mapped in a standard software discoverable way. The modules available are: i) Pokey! ii) SID including decent filter for 6581 and 8580 as used in the C64. iii) YM2149 (PSG) as used in the ST iv) Covox v) Covox extension that can play samples from internal fpga ram, compressed using adpcm. Like Paula on the Amiga but uses its own memory due to system memory constraints. vi) PS2 keyboard support with fixed Atari key positional mapping (like the EclaireXL) vii) SPDIF output viii) Analog output ix) Flash support (needed for data for some of the above, otherwise used to store settings) There all take space, so you can decide what to enable based on the size of the FPGA you fit. The 'full' setup I used on the largest 10M16 (recommended) ones is quad pokey, dual sid, dual psg, covox with sample, spdif, analog, ps2 As to what v1-v4 bring, I'll post a small table shortly.

Should just be able to: svn checkout http://www.64kib.com/atarixlfpga_svn/trunk/atari_800xl/

The audio ac coupling caps are already included (since v2b). Regarding pins, on the top header there are four pins: GND SPDIF LEFT RIGHT On the bottom header the pins are: 2 4 6 8 10 1 3 5 7 9 I was planning this: 9= SIO audio in 1=A4 2=A5 3=A6 4=A7 5=PS2clk 6=PS2dat 7=GTIA audio 1-8 and 10 can be redefined here: http://www.64kib.com/atarixlfpga_svn/trunk/atari_800xl/atari_chips/pokeyv2/build.sh See:10M08_fullv4_stereo Re U1MB: It has a plugin now and talks to pokeymax directly, no need for a wire.

Found a few more minutes! Popped the level shifters on, not all plain sailing with these small items: A bit of flux and braid and its all good: Careful, these go on two different ways around Couldn't resist popping pins on and putting it in the Atari. No sound circuits yet or paddle supporting parts etc. Result: Atari still boots to basic, keyboard not working, sio not working - see some speed switches only on aspeqt. Not too surprised for the first test, but pleased it boots at least!

I committed a first pass of the hdl support to the repository, untested as yet. It synthesizes, that is all that can be said! Added pokeymaxv4.qsf with pin definitions based on the schematic Added pokeymaxv4.sdc, just a copy of v3. Will need updating. Added the 3 features to the pokeymax.vhd as generics: iox vs direct keyboard k/kr support, paddle via external/internal comparators, adc (not yet wired to mixer) Also just got a new disk for my server, so hopefully it'll stop going down all the time!

xray machine, or in my case ... pray! I'll be back with more updates next week, no time to work on this after tonight for a few days. I ran into a fun problem though with the paddle inputs. I used LVDS inputs for the comparator and thought I could also set them to outputs to reset the paddle. Though... no luck so far. Seems like it should be possible though according to this: http://www.altera.com/literature/an/an522.pdf

Put this little chap on (tinned pads on the pcb with lead free + flux, cleaned up, then simply placed this on and heated it up with hot air): Here we are: Then connected 5V and the usb blaster and ran jtagconfig and ... its on jtag at least: jtagconfig 1) USB-Blaster [1-5.1] 031820DD 10M08SA(.|ES)/10M08SC It lives, to some degree at least!

Before work this morning I finished the supporting parts for the FPGA: All decoupling caps: C1,C2,C5,C6,C11 - all 0.1uF Ferrite bead for 3.3v analog from 3.3v JTAG and pull ups to get the FPGA to configure. R3 is 1K, R1,R2,R4,R5 are 10K. Next its the FPGA, 169 pins of BGA goodness!

The MAX10 and the level shifters run on 3.3v, that is why I need that. One nice feature of this version of the MAX10 is that it is single supply, so I only need to provide 3.3v. Unlike the Cyclone V in the EclaireXL for example which needs 3.3v, 2.5v and 1.1v. I added an extra 2.5v on here though so I can run the LVDS inputs as comparators for the paddle inputs. Also I use an LVDS input as an ADC for audio input. I think I tested it and it does actually work with 3.3v, but Intel said in a thread on their forum that might damage it so thought I'd better include a regulator. Anyway power is working, onto the next step.

I received the boards: So, started making it. The 3.3v regulator is a bit small. A bit of flux, tinned the pads, held in place with tweezers and a bit of hot air: This is enough to get 3.3v working. Regulator, two caps and and an inductor. Couple of wires to test it and it worked: Then put on the 2.5v regulator and a decoupling cap because it was next to it: Oh and I also got some jtag adaptors: Also getting there with the pin assignments file, not quite ready to commit yet though.

Found the first mistake, I put this 8-pin header on the BOM when I needed a 10 pin. Doh! https://www.digikey.ch/en/products/detail/adam-tech/PH2RA-08-UA/9830984

I'm going to receive the pokeymax v4 boards tomorrow and, all being well, get them running over the next week or so. Since the project is now more open than before I'm going to post some details of what needs doing for this here along with progress. Feel free to chime in with comments. Status: i) Boards ordered from PCBWay. http://www.64kib.com/atarixlfpga_svn/trunk/atari_800xl/atari_chips/hardware/pokeymaxv4/2layer030drill/ ii) Parts ordered from Digikey - arrived. https://www.digikey.ch/en/mylists/list/MZC8NOSXG1. I grabbed 5 copies (it's cheaper in volume) and removed four of the FPGAs. I'm planning to transfer and reball some of the FPGAs from my other boards. Also I already have a spare new 10M08 floating around. TODO: a) svn checkout the HDL from http://www.64kib.com/atarixlfpga_svn/trunk/atari_800xl/ b) Modify atari_chips/pokeyv2/ to add the v4 board: Copy the qsf file and correct/add the pin assignments from the schematic. Set up the paddle pins as LVDS. Add a feature to pokeymax.vhd to directly use the fpga io for the keyboard instead of using the io expander chip over i2c. Add a feature to pokeymax.vhd to directly reset the paddle pins Copy the ADC input feature from the sidmax.vhd to pokeymax.vhd, add it to the pokey mixer. Update build.sh adding a v4 board and enabling these features Synthesise the logic by sourcing the quartus settings file then running build.sh with the new configuration. c) Assemble a board bit by bit checking functionality Visual inspection Check for shorts on the power nets Solder on the regulator, its support parts (caps, inductors) and ferrite bead for 3.3v analog. Power the board and check power rail voltages. Solder on the FPGA, FPGA core support parts (Pull ups etc), FPGA jtag support parts. Connect the JTAG, can I see the FPGA? Modify my JTAG boundary scan script to check for any shorts under the FPGA. Solder on the rest of the SMD parts: 5V/3.3v level converter chips, paddle level potential divider, adc coupling cap and dc bias, output op amp and feedback parts, output audio coupling caps Solder on the pin header strips, the audio output header and the io header. Put it into the Atari! Power it on, flash the new core, power off/on and pray! Debug, goto 11.

Yes, those are fine