sup8pdct

Curt is right. The first 16K is 600xl internal ram then the rest is on the 1064. The 600xl has an extra chip 74ls32 that does that. When 64K is added internally, the 32 can be removed and a jumper must be placed between pins 8 and 10 . Also the 1064 has the same chip that selects itself after the first 16K. Don't take my word for it, check out the schematics for the 1064 and 600XL @ jsobola.republika.pl/schematy.htm Also the 1064 doesn't appear to pull any control line low, not according to the schematic, so a 1064 on an 800xl will only suck power if the power lines are restored and mirror the internal ram after the first 16K. James

I made one of these way back in the early 90's. Just have 2 switches. Don't have writers tool tho. James

The one with a case, do the sides of the case slot into plastic clips? if not, then remove the covers and put spacer back in. Else secure other 2 boards using any means available. I used small pieces of styrofoam to jam the sides to the case making sure none of the chips are touching the chips. I know from experience that ram boards not secured with spacer or other means will move around while typing causing exactly what you are seeing. James

Are the ram boards secured properly? It sounds like the ram boards are moving around while you are typing away. There was an update where all 800's were equipped with 48K, all boards had no covers and a black plastic spacer sat across all boards front to back to stop them moving around. There was also a service bulletin about removal of the card covers due to heat build up. James

Yes, this is normal. The cart which happens to be 8K occupies the same address space as the top 8K of ram. When a cart is inserted, the ram in that same space cannot be selected, unless the cart is a special bank select type.(not many of those). Please note there are 16K carts as well which means 16K of ram is lost if one is plugged in. 37902 you see free in basic is actually about 38K. Ram needs to be used for OS stuff, basic pointers and screen ram. If you have loaded a dos, it could take anywhere from 3K to 10K of ram (depending on dos used and what extra goodies you have in the 800). The file version of salt is actually a dump of the cartridge rom. It is loaded into ram at the same address as the original rom and a pointer changed. Salt thinks it is running from rom so only expects to see and tests for 40K of ram James

Here is dissembly listing from bob1200xl roms. Have added some comments from orignal source from curt. enjoy ; ; User equates ; TIMR2 = $039F TIMR3 = $039E TIM1R = $0395 PIA1EC = $0384 PBDDR1 = $0383 PORTB1 = $0382 PADDR1 = $0381 PORTA1 = $0380 TIMR22 = $029F TIMR2R = $0295 PIA2EC = $0284 PBDDR2 = $0283 PORTB2 = $0282 PADDR2 = $0281 PORTA2 = $0280 TIMR23 = $021F TIMR3R = $0215 PIA3EC = $0204 PBDDR3 = $0203 PORTB3 = $0202 PADDR3 = $0201 PORTA3 = $0200 SSDA1 = $0101 SSDA0 = $0100 CMPLT = $43 ;C complete ; ; Code equates ; ZPRL = $0000 ZP80 = $0080 ZP91 = $0091 FRMCRC = $00A0 ZPCRC = $00AE ZPNTL = $00C0 ZPNTH = $00C1 SCTPT = $00F6 CRCLP = $00F7 IDAM = $00F8 TRKNO = $00F9 BYTE00 = $00FA SCTNO = $00FB BYTE01 = $00FC CRC1 = $00FD CRC2 = $00FE BYTE4E = $00FF L0106 = $0106 L0119 = $0119 L0131 = $0131 RAM3 = $0180 STPNT = $0180 UNITNB = $0181 ;DRIVE UNIT # (ASCII) CTLCMD = $0182 ;CONTROLLER COMMAND AUX1 = $0183 ;LSB OF 16-BIT LOGICAL SECTOR # AUX2 = $0184 ;MSB OF 16-BIT LOGICAL SECTOR # RCDCSM = $0185 ;COMMAND FRAME CHECKSUM TMPOUT = $0186 ;ALL SERIAL OUTPUT SHIFTED FROM THIS ADDR DICKSM = $0187 ;DATA FIELD CHECKSUM TEMP STFLG2 = $0190 ;BOTTOM DRV STATUS FLAGS DEVST2 = $0191 ;BOTTOM DRV XTRA STATUS WCTLB2 = $0192 ;BOTTOM DRV WORST CASE TIMEOUT (LSB) WCTMB2 = $0193 ;DELAY (MSB) EGON = $0194 ;ERASE GATE TURN ON CODE WGOFF = $0195 ;ERASE GATE TURN ON CODE BAKER = $0196 ;CRC GENERATION SCRATCH 1 ABLE = $0197 ;CRC GENERATION SCRATCH 2 GAPBYT = $0198 ;BYTE INIT'D TO $4E FOR CRC WRITE DH80T = $0199 ;DOUBLE HEAD & 80 TRK TEST BYTE STPDIR = $019D RDCRC2 = $019E RDCRC1 = $019F STPNB2 = $01A0 ;# OF STEPS TO DESIRED TRACK, BOTTOM DRV PRTRK2 = $01A1 ;PRESENT TRACK #, BOTTOM DRV SPSDC2 = $01A2 ;LOOP COUNTER FOR BOTTOM DRV SHUTDOWN TIMER SPMDC2 = $01A3 SCRT1 = $01A4 SCRT2 = $01A5 SCTTBL = $01A6 ;START OF 11-BYTE ID FIELD SPMDLC = $01B1 ;1 SEC LOOP COUNT FOR SPM SHUT-OFF (4 * 125 MS) STPSCR = $01CD ;STEP ROUTINE SCRATCH PRSTRK = $01CE ;PRESENT TRACK #, TOP DRV STPNBR = $01CF ;# OF STEPS TO DESIRED TRK #, TOP DRV STFLGS = $01D0 ;STATUS FLAGS (TOP DRV) SHIPPED TO COLLEEN DEVSTA = $01D1 ;TOP DRV EXTRA STATUS WCTLSB = $01D2 ;WORST CASE TIMEOUT SENT TO COLLEEN (LSB) WCTMSB = $01D3 ;(MSB) PACNTR = $01D4 ;R/W ERROR RETRY COUNT SSCTMS = $01D7 ;MSB,16-BIT LOGICAL SECTOR # (SECTOR BREAKDOWN) SSCTLS = $01D8 ;LSB, SAVED BY SEC BRKDWN BUT NOT USED TRKNBR = $01DA ;TRACK # COMPUTED IN SECTOR BREAK-DOWN SCTNBR = $01DB ;SECTOR # FROM SECTOR BREAK-DOWN INMODE = $01DC ;INTERNAL MODE REGISTER ; ; BIT DEFINITIONS FOR INMODE: ; ; 7 - 19.2/38.4 KBAUD SERIAL DATA RATE (19.2 KBAUD = 1) ; 6 - DRIVE SELECT (TOP DRIVE = 1, BOTTOM DRIVE = 0) ; 5 - SIDE SELECT (FOR DUAL HEADED DRIVES, SIDE0=0, SIDE1=1) ; 4 - N/A ; 3 - N/A ; 2 - SPM2 NOT ON >1 SEC IF SET ; 1 - N/A ; 0 - IF SET, WITHIN COMMAND INPUT ROUTINE (ALSO USED FOR DATA/CMD FRAME ; CHECKSUM ROUTINE SELECT) ; ; BIT EQUATES FOR INMODE: ; INSTAT = $01DD ;INTERNAL STATUS REGISTER ; ; BIT DEFINITIONS FOR INTERNAL STATUS REGISTER: ; ; 7 - RECEIVING NEW COMMAND WORDS IF SET ; 6 - BUSY, SET WHENEVER GOING TO A ROUTINE THAT WILL KEEP US ; AWAY FROM THE COMMAND FRAME MONITOR MORE THAN 400 MS ; 5 - SHUTDOWN IN PROGRESS, WHEN SET INDICATES CONTROL SHOULD RTS ; FROM MAIN MONITOR--DOES NOT INDICATE 400 MS ABSENCE ; 4 - NO DISK ; 3 - FORMAT ERROR IF SET, AND READ AFTER WRITE FLAG! ; 2 - SPINDLE MOTOR HAS NOT BEEN ON 1 SEC IF SET ; 1 - COMMAND RECEIVE ERROR IF SET ; 0 - IF SET, COLLEEN HAS NOT BEEN WITH US 100 MS+ ; INSCRT = $01DE ;LAST INDEX +1 TO TERMINATE INPUT OR CHECKSUM TMRSCR = $01DF ;TIMER SCRATCH FSCTBP = $01E0 ;FORMAT VERIFY ERROR RETRY COUNT BFRPNT = $01E1 ;FORMAT BAD SECTOR # BUFFER INDEX TMPSB = $01E3 ;*2 TEMP STORAGE FOR SECTOR BUILD-UP MSBSB = $01E4 ;MSB FOR SECTOR BUILD-UP CSSCRT = $01E5 YSAVE = $01E6 CTABL = $01E8 ;JUMP INDIRECT ADDRESS FOR COMMAND INTERPRETER CTABH = $01E9 ;MSB SPMSDC = $01EB ;LOOP COUNTER FOR TOP DRV SHUTDOWN TIMER ; unused jump addresses XTND1 = $0803 XTND3 = $0809 XTND4 = $080C XTND5 = $080F XTND6 = $0812 ;SECTOR # VALIDITY TEST, > 720 XTND7 = $0815 XTND8 = $0818 XTND9 = $081B XTND10 = $081E ;SIDE 2 CLRS? XTND11 = $0821 XTND13 = $0827 XTND14 = $082A ; ; Start of code ; *= $0800 ; ; **************************** ; POWER-ON INTIALIZATION ; **************************** cld ; D8 lda #$1B ; A9 1B ldx #$FF ; A2 FF txs ; 9A sta PORTA2 ; 8D 80 02 stx PORTB2 ; 8E 82 02 stx PADDR2 ; 8E 81 02 stx PBDDR2 ; 8E 83 02 lda #$00 ; A9 00 sta PORTA1 ; 8D 80 03 sta PORTA3 ; 8D 00 02 sta PORTB3 ; 8D 02 02 lda #$1A ; A9 1A sta PADDR3 ; 8D 01 02 ldx #$6A ; A2 6A stx PADDR1 ; 8E 81 03 L0827 ldx #$3C ; A2 3C stx PBDDR1 ; 8E 83 03 inx ; E8 stx PBDDR3 ; 8E 03 02 ldx #$30 ; A2 30 stx PORTB1 ; 8E 82 03 stx PORTB3 ; 8E 02 02 stx PIA1EC ; 8E 84 03 stx PIA3EC ; 8E 04 02 stx PIA2EC ; 8E 84 02 ldx #$68 ; A2 68 stx PORTA1 ; 8E 80 03 lda #$D0 ; A9 D0 sta SSDA0 ; 8D 00 01 lda #$9B ; A9 9B sta SSDA1 ; 8D 01 01 lda #$D2 ; A9 D2 sta SSDA0 ; 8D 00 01 lda #$00 ; A9 00 sta SSDA1 ; 8D 01 01 ldx #$7F ; A2 7F L085C sta ZPRL,X ; 95 00 sta ZP80,X ; 95 80 sta RAM3,X ; 9D 80 01 cmp ZPRL,X ; D5 00 bne L0875 ; D0 0E cmp ZP80,X ; D5 80 bne L0875 ; D0 0A cmp RAM3,X ; DD 80 01 bne L0875 ; D0 05 dex ; CA bpl L085C ; 10 E9 bmi L0884 ; 30 0F L0875 lda #$08 ; A9 08 L0877 sta PORTA3 ; 8D 00 02 L087A dex ; CA bne L087A ; D0 FD iny ; C8 bne L087A ; D0 FA eor #$08 ; 49 08 bpl L0877 ; 10 F3 ;################################################### L0884 lda #$05 ; A9 05 sta INSTAT ; 8D DD 01 lda #$C4 ; A9 C4 sta INMODE ; 8D DC 01 lda #$27 ; A9 27 sta PRTRK2 ; 8D A1 01 sta PRSTRK ; 8D CE 01 lda #$04 ; A9 04 sta SPMDLC ; 8D B1 01 lda #$E0 ; A9 E0 sta WCTLSB ; 8D D2 01 sta WCTLB2 ; 8D 92 01 lda #$00 ; A9 00 sta WCTMSB ; 8D D3 01 sta WCTMB2 ; 8D 93 01 sta DEVSTA ; 8D D1 01 sta DEVST2 ; 8D 91 01 sta SPMSDC ; 8D EB 01 sta SPSDC2 ; 8D A2 01 ; copy ID field into ram ldx #$0A ; A2 0A L08B9 lda IDFLD,X ; BD 9D 17 sta SCTTBL,X ; 9D A6 01 dex ; CA bpl L08B9 ; 10 F7 inx ; E8 ldy #$60 ; A0 60 lda PORTB3 ; AD 02 02 and #$02 ; 29 02 bne L08CF ; D0 03 jsr XTND14 ; 20 2A 08 GO TO XTRA ROM FOR MOR DH/96 ;TPI AND 38K TSTING L08CF sty STFLGS ; 8C D0 01 sty STFLG2 ; 8C 90 01 stx DH80T ; 8E 99 01 jsr CLRST ; 20 4C 15 jsr CLRST2 ; 20 55 15 ; ; ***************************** ; WARM START RE-ENTRY POINT ; ***************************** ; INIT2 ldx #$FF ; A2 FF txs ; 9A lda #$F7 ; A9 F7 jsr CLRST1 ; 20 4E 15 CLEAR TOP DRV WP STATUS lda #$F7 ; A9 F7 jsr CLRS12 ; 20 57 15 ldx #$08 ; A2 08 lda PORTA1 ; AD 80 03 tay ; A8 and #$10 ; 29 10 beq L08F9 ; F0 04 txa ; 8A jsr ORSTF ; 20 2D 15 SET IT IN TOP DRV STATUS FLAGS L08F9 tya ; 98 and #$01 ; 29 01 beq L0902 ; F0 04 txa ; 8A jsr ORSTF2 ; 20 45 15 SET IT IN BOTTOM DRV STATUS FLAGS L0902 ldx #$1B ; A2 1B stx PORTA2 ; 8E 80 02 lda PORTA3 ; AD 00 02 and #$E7 ; 29 E7 sta PORTA3 ; 8D 00 02 bit DH80T ; 2C 99 01 bpl L0917 ; 10 03 jsr XTND10 ; 20 1E 08 GO TO XTRA ROM FOR SIDE2 CLRS L0917 lda #$40 ; A9 40 jsr ORINMD ; 20 73 15 lda #$27 ; A9 27 jsr CSTEP ; 20 3E 17 CALC STPS NEEDED FOR TRK 39 DRV sty STPNBR ; 8C CF 01 lda #$BF ; A9 BF jsr ANDNMD ; 20 7A 15 SET FOR DRIV2 SRVICE lda #$27 ; A9 27 jsr CSTEP ; 20 3E 17 sty STPNB2 ; 8C A0 01 lda #$20 ; A9 20 jsr ORINST ; 20 34 15 SET SHUTDN BIT IN INTRNL STAT lda #$F7 ; A9 F7 jsr ANINS ; 20 6C 15 L093B ldx SPMSDC ; AE EB 01 beq L0949 ; F0 09 lda #$FF ; A9 FF sta TIMR23 ; 8D 1F 02 dex ; CA stx SPMSDC ; 8E EB 01 L0949 ldx SPSDC2 ; AE A2 01 beq L0957 ; F0 09 lda #$FF ; A9 FF sta TIMR23 ; 8D 1F 02 dex ; CA stx SPSDC2 ; 8E A2 01 L0957 ldx SPMSDC ; AE EB 01 bne L096B ; D0 0F ldx #$80 ; A2 80 ldy STPNBR ; AC CF 01 beq L099B ; F0 38 BRNCH IF NO STPS NEEDED ON DRV1 jsr STEP1 ; 20 8D 10 STEP DRV1 AND SAV STP CNTR beq L099B ; F0 33 L0968 sty STPNBR ; 8C CF 01 L096B ldx SPSDC2 ; AE A2 01 bne L097F ; D0 0F ldx #$80 ; A2 80 ldy STPNB2 ; AC A0 01 beq L09A8 ; F0 31 jsr L10C6 ; 20 C6 10 beq L09A8 ; F0 2C L097C sty STPNB2 ; 8C A0 01 L097F ldx SPMSDC ; AE EB 01 bne L09B5 ; D0 31 ldx SPSDC2 ; AE A2 01 bne L09B5 ; D0 2C ldx STPNBR ; AE CF 01 bne L09BD ; D0 2F ldx STPNB2 ; AE A0 01 bne L09BD ; D0 2A L0993 lda #$DF ; A9 DF jsr ANINS ; 20 6C 15 jmp MMON ; 4C D6 09 L099B lda #$68 ; A9 68 sta PORTA1 ; 8D 80 03 lda #$04 ; A9 04 jsr ORINST ; 20 34 15 jmp L0968 ; 4C 68 09 L09A8 lda #$00 ; A9 00 sta PORTA3 ; 8D 00 02 lda #$04 ; A9 04 jsr ORINMD ; 20 73 15 jmp L097C ; 4C 7C 09 L09B5 bit TIMR3R ; 2C 15 02 bmi L09C8 ; 30 0E jsr MMON ; 20 D6 09 L09BD bit TIM1R ; 2C 95 03 bmi L0957 ; 30 95 jsr MMON ; 20 D6 09 jmp L09BD ; 4C BD 09 L09C8 bit TIM1R ; 2C 95 03 bmi L09D3 ; 30 06 jsr MMON ; 20 D6 09 jmp L09C8 ; 4C C8 09 L09D3 jmp L093B ; 4C 3B 09 ; ; **************** ; MAIN MONITOR ; **************** ; ; MONITORS THE READY PORT FOR ; COLLEEN PRESENCE. MONITORS THE CMND ; FRAME,BRINGS IN 5 BYTE COMMAND, CHE ; CKS FOR VALID CHECKSUM, CHECKS IF ; CMND ADDRESS IS FOR FLOPPY BEFORE ; GOING TO CMND INTERPRET ROUTINE ; MMON lda PORTB1 ; AD 82 03 lsr A ; 4A lsr A ; 4A bcs L0A0F ; B0 32 lda INSTAT ; AD DD 01 lsr A ; 4A bcs L0A02 ; B0 1F bit PORTB1 ; 2C 82 03 bvc L09F7 ; 50 0F bit INSTAT ; 2C DD 01 bvc L0A17 ; 50 2A lda #$A4 ; A9 A4 jsr TIMER ; 20 12 15 bit PORTB1 ; 2C 82 03 bvs L0A17 ; 70 20 L09F7 lda INSTAT ; AD DD 01 and #$60 ; 29 60 bne L0A01 ; D0 03 jmp MMON ; 4C D6 09 L0A01 rts ; 60 L0A02 lda #$A4 ; A9 A4 jsr TIMER ; 20 12 15 lda #$FE ; A9 FE jsr ANINS ; 20 6C 15 jmp MMON ; 4C D6 09 L0A0F lda #$01 ; A9 01 jsr ORINST ; 20 34 15 jmp L09F7 ; 4C F7 09 L0A17 lda #$80 ; A9 80 jsr ORINST ; 20 34 15 ldx #$00 ; A2 00 lda #$05 ; A9 05 sta INSCRT ; 8D DE 01 jsr CINPUT ; 20 B6 11 ;################################################# ; MAIN MONITOR (CONTINUED) ;################################################# ldx #$00 ; A2 00 dec INSCRT ; CE DE 01 jsr CDCKSM ; 20 D9 15 beq L0A35 ; F0 05 lda #$02 ; A9 02 jsr ORINST ; 20 34 15 L0A35 lda PORTA3 ; AD 00 02 lsr A ; 4A bcc L0A6C ; 90 31 ldx #$31 ; A2 31 asl A ; 0A RESTORE PORTA3 bmi L0A42 ; 30 02 IF DRV ADDR #1 IS SET, BRANCH ldx #$35 ; A2 35 L0A42 cpx UNITNB ; EC 81 01 beq L0A65 ; F0 1E BRNCH IF DRIV ADDRESED IS ODD inx ; E8 cpx UNITNB ; EC 81 01 beq L0A5A ; F0 0D BRNCH IF EVEN DRIV ADRESED IS U L0A4D bit PORTB1 ; 2C 82 03 bvs L0A4D ; 70 FB SPIN TIL COMND FRAM GONE lda #$7D ; A9 7D CLR REC NEW CMND AND jsr ANINS ; 20 6C 15 CS ERR BITS jmp MMON ; 4C D6 09 RETURN TO MON SER BUS L0A5A lda #$BF ; A9 BF jsr ANDNMD ; 20 7A 15 UPDATE INMODE FOR DRIV 2 SEL L0A5F jsr L0A75 ; 20 75 0A GO COMMAND INTERP---FOR US jmp MMON ; 4C D6 09 L0A65 lda #$40 ; A9 40 jsr ORINMD ; 20 73 15 UPDATE INMODE FOR DRIV 1 SEL bne L0A5F ; D0 F3 L0A6C ldx #$33 ; A2 33 asl A ; 0A bmi L0A42 ; 30 D1 ldx #$37 ; A2 37 bne L0A42 ; D0 CD ; *********************** ; COMMAND INTERPRETER ; *********************** L0A75 lda INSTAT ; AD DD 01 CHECK RECEIVE ERROR FLAG and #$02 ; 29 02 MASK OFF OTHERS bne CMD2 ; D0 1E IF CHECKSUM ERROR, GOTO INVALID CMD NAK lda CTLCMD ; AD 82 01 ELSE, FETCH CMD CODE FROM CMD FRAME ldx #$0A ; A2 0A MAXIMUM INDEX INTO LEGAL CMD CODE TABLE L0A81 cmp TABB,X ; DD B2 0A COMPARE REC'D CMD W/LEGAL CMD LIST beq L0A8B ; F0 05 GOT A MATCH, GO EXECUTE dex ; CA ELSE, DECREMENT INDEX bpl L0A81 ; 10 F8 LOOP IF ANY LEGAL ENTRIES LEFT bmi CMD2 ; 30 0F NO, UNCONDITIONAL SEND INVALID CMD FRAME L0A8B lda TABL,X ; BD BD 0A YES, FETCH LO ADDR OF ROUT sta CTABL ; 8D E8 01 SAVE IN INDIRECT JUMP VECTOR lda TABH,X ; BD C8 0A FETCH HI ADDR TOO sta CTABH ; 8D E9 01 SAVE IN HI ADDR OF VECTOR jmp (CTABL) ; 6C E8 01 JUMP TO SELECTED COMMAND ROUTINE CMD2 lda #$01 ; A9 01 SET INVALID CMD FRAME FLAG jsr OR0STX ; 20 1E 15 IN PRESENT DRIVE STATUS BYTE jsr MFUTST ; 20 12 11 SET SPM ON BIT IN STATUS TOO L0AA2 bit PORTB1 ; 2C 82 03 bvs L0AA2 ; 70 FB WAIT TIL CMD FRAME GONE lda #$4E ; A9 4E LOAD NAK CODE jsr SAA2 ; 20 82 17 SEND IT TO COLLEEN lda #$FD ; A9 FD CLEAR CMD RECEIVE ERROR FLAG jsr ANINS ; 20 6C 15 IN INTERNAL STATUS REGISTER rts ; 60 RETURN TO MAIN MONITOR ; TABB .byte $20 .byte "!PQRSTUVWX" ;TABL .byte $21,$1E,$D8,$68,$78,$BD,$76,$70 ; .byte $D3,$D3,$8C ;TABH .byte $0D,$0E,$0A,$0D,$0C,$0D,$0D,$10 ; .byte $0A,$0A,$0D TABL: .BYTE <DOWNLD ;DOWN LOAD .BYTE <FRMT ;FORMAT .BYTE <WRITE1 ;WRITE, NO VERIFY .BYTE <RDSPN ;READ SPIN .BYTE <READ ;READ SECTOR .BYTE <STCMD ;STATUS COMMAND .BYTE <RDADR ;READ FROM ADDRESS .BYTE <MOTRON ;MOTOR ON DELAY .BYTE <WRITE ;VERIFY ENTERS AT WRITE .BYTE <WRITE ;WRITE/VERIFY .BYTE <CMDX ;cOMMAND X WHAT DOES IT DO? ; TABH: .BYTE >DOWNLD .BYTE >FRMT .BYTE >WRITE1 .BYTE >RDSPN .BYTE >READ .BYTE >STCMD .BYTE >RDADR .BYTE >MOTRON .BYTE >WRITE .BYTE >WRITE .BYTE >CMDX ;#################################################### ; Write ;#################################################### WRITE lda #$08 ; A9 08 jsr ORINST ; 20 34 15 SET INSTAT FOR READ AFTR WRITE ; WRITE, NO VERIFY ENTRY POINT: WRITE1 jsr TSN ; 20 A7 15 GO INSUR RECVD SECTR NUMBR VAL bcc L0AE0 ; 90 03 BRNCH IF SCTOR VALID jmp L0BBD ; 4C BD 0B L0AE0 lda #$4E ; A9 4E wr10 sta GAPBYT ; 8D 98 01 jsr SETSUP ; 20 39 12 beq L0AED ; F0 03 BRNCH IF NO STEPS NEEDE jsr STEP ; 20 88 10 L0AED sty STPNBR ; 8C CF 01 SAV TEMP NUMBR STEPS NEEDED stx STPDIR ; 8E 9D 01 SAV STEP DIRECT TEMP jsr INPUT ; 20 59 16 GO INPUT DATA FIELD,COMP,CALC- ; -ULATE CS AND COMPAR CS'S beq L0B00 ; F0 08 BRNCH IF NO CS ERR L0AF8 lda #$12 ; A9 12 L0AFA jsr OR0STX ; 20 1E 15 SET SPM AND DATA FRAME ERROR FLGS jmp INIT2 ; 4C DE 08 L0B00 jsr SAA1 ; 20 80 17 GO ACK DATA FIELD ldx STPDIR ; AE 9D 01 ldy STPNBR ; AC CF 01 jsr STPTST ; 20 5E 17 GO EXECUT STEPS IF NEEDED jsr SPMDY ; 20 B2 13 INSURE SPM STABL lda CTLCMD ; AD 82 01 cmp #$56 ; C9 56 CHECK FOR VERIFY ONLY bne L0B1C ; D0 06 BRNCH IF HERE FOR WRITE jsr CRCSUP ; 20 0F 12 jmp L0BA0 ; 4C A0 0B GO DO VERFY L0B1C jsr WPTST ; 20 5E 15 beq L0B24 ; F0 03 BRNCH IF NOT WP jmp L0BC5 ; 4C C5 0B L0B24 jsr CRCSUP ; 20 0F 12 L0B27 ldy #$00 ; A0 00 Y SET TO INDICAT PASS jsr SYNC ; 20 65 14 THRU SYNC LOOP FOR IDAM bne L0B36 ; D0 08 BRNCH IF HAV SYNC lda #$10 ; A9 10 jsr ORST1 ; 20 81 15 UPDATE DEVICE STAT FOR NO ID jmp L0BCF ; 4C CF 0B L0B36 jsr FWSL ; 20 F1 15 ldx #$0C ; A2 0C jsr FSL ; 20 61 10 ldx EGON ; AE 94 01 stx PORTB2 ; 8E 82 02 ldx #$05 ; A2 05 jsr FSL ; 20 61 10 jsr FWSL1 ; 20 3F 16 GO XMIT REMAINDR OF DATA FIELD ; GAP AND ID sec ; 38 CARRY MUST REFLECT LST BIT XMIT ; ED. ldx #$00 ; A2 00 CLR BUFR POINTR jsr WSL ; 20 DC 12 GO XMIT 128 BYTE BUFR THRU ; CLK/DTA LOOKUP TBL ; ; *************** ; WRITE CRC'S ; *************** ; ; (CALLED ONLY ONCE BY WRITE ROUTINE, COULD BE "IN-LINE") ; ; WCRC WRITES 2 CRC'S FOR DATA FIELD ; DURING WRITE ROUT. NOT USED B ; BY FORMAT ROUT ; ldx #$7D ; A2 7D INDEX FOR 2 BYTES L0B54 bit SSDA0 ; 2C 00 01 bvc L0B54 ; 50 FB POLL SSDA FOR XMIT REG AVAIL lda L0119,X ; BD 19 01 ror A ; 6A lsr A ; 4A lsr A ; 4A lsr A ; 4A tay ; A8 lda CDLT,Y ; B9 B9 17 sta SSDA1 ; 8D 01 01 lda L0119,X ; BD 19 01 and #$1F ; 29 1F tay ; A8 lsr A ; 4A lda CDLT,Y ; B9 B9 17 sta SSDA1 ; 8D 01 01 inx ; E8 bpl L0B54 ; 10 DD ; L0B77 lda SSDA0 ; AD 00 01 and #$08 ; 29 08 beq L0B77 ; F0 F9 BRNCH TIL TUF SET IN STATREG lda #$D3 ; A9 D3 sta SSDA0 ; 8D 00 01 lda PORTA1 ; AD 80 03 REST XMIT and #$DF ; 29 DF sta PORTA1 ; 8D 80 03 REST CTS FF ora #$20 ; 09 20 sta PORTA1 ; 8D 80 03 SET CTS FF lda WGOFF ; AD 95 01 sta PORTB2 ; 8D 82 02 jsr EGOFF ; 20 29 12 lda INSTAT ; AD DD 01 and #$08 ; 29 08 beq L0BAD ; F0 0D BRNCH IF NO READ CHK REQIRED L0BA0 lda #$52 ; A9 52 sta CTLCMD ; 8D 82 01 jsr RDWRLT ; 20 70 11 jsr L0BDF ; 20 DF 0B GO RD SCTR TO VRIFY bcs L0BDA ; B0 2D BRNCH IF BAD WRITE VRIFY L0BAD lda #$10 ; A9 10 jsr OR0STX ; 20 1E 15 UPDTE STAT FOR GOOD WRITE jsr L0D1B ; 20 1B 0D lda #CMPLT ; A9 43 Complete L0BB7 jsr SAA2 ; 20 82 17 OUTPUT TO COLLEEN jmp INIT2 ; 4C DE 08 GOTO SHUTDOWN ; L0BBD lda #$F7 ; A9 F7 jsr ANINS ; 20 6C 15 jmp CMD2 ; 4C 9A 0A ; L0BC5 lda #$1C ; A9 1C SET STATUS FOR WP L0BC7 jsr OR0STX ; 20 1E 15 lda #$45 ; A9 45 SET A FOR ERR jmp L0BB7 ; 4C B7 0B L0BCF ldx PACNTR ; AE D4 01 beq L0BDA ; F0 06 BRNCH TO GIV UP WRITE ATMPT jsr ERRTRY ; 20 33 11 REPOSITON HEAD jmp L0B27 ; 4C 27 0B REATMPT WRITE L0BDA lda #$14 ; A9 14 jmp L0BC7 ; 4C C7 0B GO SET STATUS FOR ERR L0BDF lda #$01 ; A9 01 sta PACNTR ; 8D D4 01 SET FOR 2 READ ATTEMPTS L0BE4 ldy #$00 ; A0 00 jsr SYNC ; 20 65 14 LOOK FOR IDAM bne L0BF0 ; D0 05 BRNCH IF HAV SYNC lda #$10 ; A9 10 jmp L0C72 ; 4C 72 0C L0BF0 jsr L0D1B ; 20 1B 0D lda #$03 ; A9 03 ldy #$01 ; A0 01 jsr SYNC01 ; 20 75 14 LOOK FOR DAM beq L0C2E ; F0 32 BRNCH IF NO SYNC ldx #$00 ; A2 00 L0BFE bit SSDA0 ; 2C 00 01 bpl L0BFE ; 10 FB lda SSDA1 ; AD 01 01 cmp #$FB ; C9 FB bne L0C2E ; D0 24 lda INMODE ; AD DC 01 lsr A ; 4A bcs L0C4F ; B0 3F BRNCH IF HERE ON FORMAT CHK lda SSDA1 ; AD 01 01 cmp ZPRL,X ; D5 00 bne L0C2E ; D0 17 BRNCH IF ONE DATA FIELD WORD ERR L0C17 inx ; E8 L0C18 bit SSDA0 ; 2C 00 01 bpl L0C18 ; 10 FB BRNCH TIL RDA lda SSDA1 ; AD 01 01 cmp ZPRL,X ; D5 00 bne L0C2E ; D0 0A inx ; E8 beq L0C35 ; F0 0E BRNCH IF ALL DATA FIELD OK lda SSDA1 ; AD 01 01 cmp ZPRL,X ; D5 00 beq L0C17 ; F0 E9 L0C2E dec PACNTR ; CE D4 01 bpl L0BE4 ; 10 B1 BRNCH TO RETRY READ CHK sec ; 38 rts ; 60 L0C35 lda SSDA1 ; AD 01 01 cmp BAKER ; CD 96 01 bne L0C70 ; D0 33 BRNCH IF CRC1 NO MATCH L0C3D bit SSDA0 ; 2C 00 01 bpl L0C3D ; 10 FB lda SSDA1 ; AD 01 01 cmp ABLE ; CD 97 01 bne L0C70 ; D0 26 jsr L0D1B ; 20 1B 0D clc ; 18 CRY=NO ERR ON RETRN rts ; 60 L0C4F lda SSDA1 ; AD 01 01 cmp #$B6 ; C9 B6 bne L0C2E ; D0 D8 BRNCH IF ERR L0C56 inx ; E8 L0C57 bit SSDA0 ; 2C 00 01 bpl L0C57 ; 10 FB lda SSDA1 ; AD 01 01 cmp #$B6 ; C9 B6 bne L0C2E ; D0 CB BRNCH IF ERR inx ; E8 beq L0C35 ; F0 CF BRNCH IF 256 BYTES CHKD lda SSDA1 ; AD 01 01 cmp #$B6 ; C9 B6 beq L0C56 ; F0 E9 BRNCH IF NO ERR jmp L0C2E ; 4C 2E 0C L0C70 lda #$08 ; A9 08 L0C72 jsr ORST1 ; 20 81 15 SET BIT IN DEVICE STATUS jmp L0C2E ; 4C 2E 0C ;################################################### ; READ ;################################################### READ jsr TSN ; 20 A7 15 TEST FOR VALID SCT NUMBR bcc L0C80 ; 90 03 jmp CMD2 ; 4C 9A 0A L0C80 jsr SETSUP ; 20 39 12 jsr STPTST ; 20 5E 17 jsr SPMDY ; 20 B2 13 GO INSUR SPM STABL L0C89 ldy #$00 ; A0 00 Y SET TO INDICAT PASS THRU jsr SYNC ; 20 65 14 SYNC LOOP FOR IDAM bne L0C95 ; D0 05 lda #$10 ; A9 10 BIT IS IN DEVSTA jmp L0D03 ; 4C 03 0D UPDATE CNTRLR STAT FOR ERR L0C95 jsr L0D1B ; 20 1B 0D ldy #$01 ; A0 01 Y SET TO INDICATE PASS THRU lda #$03 ; A9 03 jsr SYNC01 ; 20 75 14 SYNC LOOP FOR DAM beq L0D06 ; F0 65 BRNCH IF NO SYNC ldx #$00 ; A2 00 CLR BUFR POINTR L0CA3 bit SSDA0 ; 2C 00 01 POLL STATREG FOR RDA bpl L0CA3 ; 10 FB lda SSDA1 ; AD 01 01 SRVICE SSDA cmp #$FB ; C9 FB FIRST WORD MUST BE DAM bne L0D06 ; D0 57 GO TO ERR IF NOT DAM lda SSDA1 ; AD 01 01 sta ZPRL,X ; 95 00 STOR IN XFER BUFR L0CB4 inx ; E8 L0CB5 bit SSDA0 ; 2C 00 01 POLL STATREG FOR RDA bpl L0CB5 ; 10 FB lda SSDA1 ; AD 01 01 sta ZPRL,X ; 95 00 STOR IN XFER BUFR inx ; E8 beq L0CCA ; F0 08 BRNCH IF BUFRS FUL lda SSDA1 ; AD 01 01 sta ZPRL,X ; 95 00 jmp L0CB4 ; 4C B4 0C L0CCA lda SSDA1 ; AD 01 01 sta RDCRC1 ; 8D 9F 01 L0CD0 bit SSDA0 ; 2C 00 01 bpl L0CD0 ; 10 FB lda SSDA1 ; AD 01 01 sta RDCRC2 ; 8D 9E 01 jsr CRCSUP ; 20 0F 12 lda RDCRC1 ; AD 9F 01 cmp BAKER ; CD 96 01 bne L0D01 ; D0 1B lda RDCRC2 ; AD 9E 01 cmp ABLE ; CD 97 01 bne L0D01 ; D0 13 L0CEE lda #$10 ; A9 10 jsr OR0STX ; 20 1E 15 RD32 lda #CMPLT ; A9 43 complete L0CF5 sta TMPOUT ; 8D 86 01 jsr SETOP ; 20 8F 17 jsr BFROUT ; 20 86 12 jmp INIT2 ; 4C DE 08 L0D01 lda #$08 ; A9 08 L0D03 jsr ORST1 ; 20 81 15 UPDATE CONTRLR STAT FOR ERR L0D06 ldx PACNTR ; AE D4 01 beq L0D11 ; F0 06 jsr ERRTRY ; 20 33 11 GO REPOSITION HEAD jmp L0C89 ; 4C 89 0C L0D11 lda #$14 ; A9 14 jsr OR0STX ; 20 1E 15 UPDATE STATUS TO REFLECT ERR lda #$45 ; A9 45 jmp L0CF5 ; 4C F5 0C L0D1B lda #$E7 ; A9 E7 jsr ANDST1 ; 20 94 15 rts ; 60 ;###################################################### ; download (different) ;###################################################### DOWNLD jsr SAA ; 20 7B 17 Send Ack ldx #$01 ; A2 01 stx SCTTBL+4 ; 8E AA 01 different from here dex ; CA stx CSSCRT ; 8E E5 01 jsr L1661 ; 20 61 16 bne L0D60 ; D0 2E same here down pha ; 48 jsr $0000 ; 20 00 00 bit INMODE ; 2C DC 01 bvc L0D4B ; 50 10 sta STFLGS ; 8D D0 01 stx DEVSTA ; 8E D1 01 sty WCTLSB ; 8C D2 01 pla ; 68 sta WCTMSB ; 8D D3 01 jmp L0D58 ; 4C 58 0D L0D4B sta STFLG2 ; 8D 90 01 stx DEVST2 ; 8E 91 01 sty WCTLB2 ; 8C 92 01 pla ; 68 sta WCTMB2 ; 8D 93 01 L0D58 lda #CMPLT ; A9 43 jsr SAA2 ; 20 82 17 jmp L0902 ; 4C 02 09 L0D60 jsr MFUTST ; 20 12 11 lda #$02 ; A9 02 jmp L0AFA ; 4C FA 0A ;####################################################### ; Read spin ;####################################################### RDSPN ldx #$52 ; A2 52 stx CTLCMD ; 8E 82 01 jsr SETSUP ; 20 39 12 jsr STPTST ; 20 5E 17 jmp L0993 ; 4C 93 09 ;####################################################### ; Read Addr. different ;####################################################### RDADR lda AUX2 ; AD 84 01 cmp #$02 ; C9 02 bcc L0D80 ; 90 03 jmp CMD2 ; 4C 9A 0A L0D80 jsr SAA ; 20 7B 17 SEND ACK ldy AUX1 ; AC 83 01 jsr L0DA3 ; 20 A3 0D jmp RD32 ; 4C F3 0C ;######################################################## ; Command X added ;######################################################## CMDX ldy #$D9 ; A0 D9 lda PORTB3 ; AD 02 02 and #$02 ; 29 02 bne L0D96 ; D0 01 sec ; 38 L0D96 lda #$17 ; A9 17 jsr L0DA3 ; 20 A3 0D bcc L0DA0 ; 90 03 jsr XTND1 ; 20 03 08 GO TO UPDATE IF X ROM INSTLD L0DA0 jmp RD32 ; 4C F3 0C L0DA3 sty ZPNTL ; 84 C0 sta ZPNTH ; 85 C1 ldy #$00 ; A0 00 L0DA9 lda (ZPNTL),Y ; B1 C0 sta $0000,Y ; 99 00 00 iny ; C8 bpl L0DA9 ; 10 F8 ldx #$01 ; A2 01 stx SCTTBL+6 ; 8E AC 01 dex ; CA stx SCTTBL+4 ; 8E AA 01 jmp RD32 ; 4C F3 0C ;####################################################### ; STATUS ;####################################################### STCMD jsr SAA ; 20 7B 17 SEND ACK L0DC0 ldx #$04 ; A2 04 bit INMODE ; 2C DC 01 bvc L0E0A ; 50 43 BRNCH IF CMND FOR DRV2 L0DC7 lda STPNBR,X ; BD CF 01 MOVE 4 BYTE STAT FOR DRV1 sta STPNT,X ; 9D 80 01 INTO MORE CONVENIENT LOC dex ; CA bne L0DC7 ; D0 F7 L0DD0 ldy #$04 ; A0 04 sty INSCRT ; 8C DE 01 jsr CDCKSM ; 20 D9 15 GEN CS ON 4 BYTE STAT sta RCDCSM ; 8D 85 01 lda #CMPLT ; A9 43 Complete sta TMPOUT ; 8D 86 01 jsr SETOP ; 20 8F 17 OPEN SERIAL OUTPUT PORT ldx #$7B ; A2 7B 5 BYTES TO SEND jsr OUTPUT ; 20 42 13 L0DE8 ldy #$0F ; A0 0F L0DEA dey ; 88 SET DELA OF bne L0DEA ; D0 FD 74 MACH CYC ldy L0106,X ; BC 06 01 106+7B=181 sty TMPOUT ; 8C 86 01 jsr OUTPUT ; 20 42 13 OUTPUT 1 BYTE inx ; E8 bpl L0DE8 ; 10 EF jsr RSTOUT ; 20 D4 12 CLOSE OUTPUT PORT bit INMODE ; 2C DC 01 bvc L0E15 ; 50 14 BRNCH IF CMND FOR DRV2 jsr CLRST ; 20 4C 15 CLR ALL STAT BUT WP jsr SPMFU ; 20 17 11 UPDATE DRV1 SPM FLG jmp INIT2 ; 4C DE 08 L0E0A lda WCTMB2-4,X ; BD 8F 01 MOVE 4 BYTE STAT FOR DRV2 sta STPNT,X ; 9D 80 01 INTO MORE CONVEINIENT LOC dex ; CA bne L0E0A ; D0 F7 beq L0DD0 ; F0 BB L0E15 jsr CLRST2 ; 20 55 15 CLR ALL BUT BASIC STATUS FOR DRiVE 2 jsr SPM2FU ; 20 25 11 UPDATE DRV2 SPM FLG jmp INIT2 ; 4C DE 08 ;#################################################### ; Format ;#################################################### FRMT jsr SAA ; 20 7B 17 SEND ACK jsr SPMON ; 20 75 13 TURN ON SPM IF NOT ALREADY jsr RDWRLT ; 20 70 11 jsr SPMDY ; 20 B2 13 INSURE MOTOR UP TO SPEED jsr WPTST ; 20 5E 15 beq L0E3D ; F0 0E TEST DISC NOT WP,IF NOT,BRNCH lda #$1C ; A9 1C jsr OR0STX ; 20 1E 15 lda #$FF ; A9 FF sta ZPRL ; 85 00 DS TRMS TO FRNT sta ZPRL+1 ; 85 01 jmp L0D11 ; 4C 11 0D L0E3D ldy #$2C ; A0 2C jsr REHME ; 20 FE 12 ldx #$FE ; A2 FE stx IDAM ; 86 F8 INIT ID FIELD LIST ldx #$4E ; A2 4E stx BYTE4E ; 86 FF ldx #$00 ; A2 00 stx BYTE00 ; 86 FA stx TRKNO ; 86 F9 stx SCTTBL+4 ; 8E AA 01 inx ; E8 stx BYTE01 ; 86 FC L0E56 jsr STSUP2 ; 20 64 12 GO TO TST FOR <20 TRK SWITCH ldx #$00 ; A2 00 stx SCTPT ; 86 F6 stx CRCLP ; 86 F7 inx ; E8 stx SCTTBL+6 ; 8E AC 01 L0E63 ldx #$F8 ; A2 F8 jsr CRCGEN ; 20 FB 13 GO GEN 2 BYTE CRC ON 5 BYTE ID ; FIELD FOR THIS TRK,SCT NUMBER. ldx CRCLP ; A6 F7 lda BAKER ; AD 96 01 sta FRMCRC,X ; 95 A0 inx ; E8 lda ABLE ; AD 97 01 sta FRMCRC,X ; 95 A0 inx ; E8 stx CRCLP ; 86 F7 ldy SCTPT ; A4 F6 ldx SCTRS,Y ; BE A8 17 bit STFLGS ; 2C D0 01 bpl L0E85 ; 10 03 jsr XTND4 ; 20 0C 08 GO TO XTRA ROM IF 38K CAPABL. not present L0E85 stx SCTTBL+6 ; 8E AC 01 inc SCTPT ; E6 F6 cpy #$12 ; C0 12 bne L0E63 ; D0 D5 BRNCH IF MOR CRCS TO DO ldx #$00 ; A2 00 stx SCTPT ; 86 F6 lda FRMCRC,X ; B5 A0 sta CRC1 ; 85 FD STORE FIRST CRC IN ID LIST inx ; E8 stx SCTNO ; 86 FB REST SCT NUMBER TO 01 lda FRMCRC,X ; B5 A0 STOR SECOND CRC IN ID LIST sta CRC2 ; 85 FE stx CRCLP ; 86 F7 SAVE CRC LIST POINTER L0E9F lda TIM1R ; AD 95 03 bpl L0E9F ; 10 FB WAIT FOR LAST STEP TO SETTLE jsr L176D ; 20 6D 17 WAIT 10MS FOR LAST STP SETL jsr FWSL ; 20 F1 15 ldx EGON ; AE 94 01 stx PORTB2 ; 8E 82 02 TURN ON ERASE GATE ldx #$FF ; A2 FF SET X AS 255 BYTE COUNTER. jsr FSL ; 20 61 10 GO XMIT 255 BYTES OF "4E" dex ; CA SETS X TO FF AS X EQUALS 00 ON ; RETURN FROM PREVIOUS JSR. jsr FSL ; 20 61 10 GO XMIT 255 BYTES OF "4E" dex ; CA jsr FSL ; 20 61 10 XMIT 255 BYTES OF "4E" ; format rest of track loop L0EBD lda #$AA ; A9 AA tay ; A8 ldx #$08 ; A2 08 jsr FSL ; 20 61 10 XMIT 8 BYTES OF "00". THIS IS S ; ECOND HALF OF GAP3. lda #$44 ; A9 44 ldy #$89 ; A0 89 ldx #$03 ; A2 03 jsr FSL ; 20 61 10 XMIT 3 BYTES OF "A1". THIS IS ; ID AM SYNC LEADER. lda #$55 ; A9 55 ldy #$54 ; A0 54 ldx #$01 ; A2 01 jsr FSL ; 20 61 10 XMIT 1 BYTE "FE". THIS IS ID AM ldx #$F9 ; A2 F9 clc ; 18 jsr WSL ; 20 DC 12 XMIT 7 BYTES OF ID FIELD THRU ; ID FIELD TABLE. lda #$92 ; A9 92 L0EDF bit SSDA0 ; 2C 00 01 bvc L0EDF ; 50 FB sta SSDA1 ; 8D 01 01 ldy #$54 ; A0 54 sty SSDA1 ; 8C 01 01 XMIT 1 BYTE "4G" FAST-LATE ldx #$12 ; A2 12 jsr FSL ; 20 61 10 XMIT 20 MORE BYTES OF "4E". THI ; S IS FIRST HALF GAP 2. inc CRCLP ; E6 F7 ldx CRCLP ; A6 F7 lda FRMCRC,X ; B5 A0 MOVE CRC1 FOR NXT SCTOR INTO sta CRC1 ; 85 FD ID FIELD LIST lda #$AA ; A9 AA tay ; A8 ldx #$0C ; A2 0C jsr FSL ; 20 61 10 XMIT 12 BYTES OF "00". THIS IS ; LAST HALF OF GAP 2. inc CRCLP ; E6 F7 ldx CRCLP ; A6 F7 lda FRMCRC,X ; B5 A0 MOVE NXT CRC2 INTO ID sta CRC2 ; 85 FE FIELD LIST lda #$44 ; A9 44 ldy #$89 ; A0 89 ldx #$03 ; A2 03 jsr FSL ; 20 61 10 XMIT 3 BYTES "A1" THIS IS DAM ; SYNC LEADER lda #$55 ; A9 55 ldy #$45 ; A0 45 inx ; E8 jsr FSL ; 20 61 10 XMIT 1 BYTE "FB" THIS IS DAM. lda #$45 ; A9 45 ldy #$14 ; A0 14 inx ; E8 jsr FSL ; 20 61 10 XMIT 1 BYTE "00" lda #$45 ; A9 45 ldx #$FF ; A2 FF XMIT 255 BYTES "00". THIS,PLUS jsr FSL ; 20 61 10 PREVIOS XMIT=128 BYTE DATA FLD lda #$45 ; A9 45 ldy #$29 ; A0 29 inx ; E8 ; XMIT 1 BYTE "48" THIS IS jsr FSL ; 20 61 10 CRC1 FOR DATA FIELD OF ALL "00" lda #$14 ; A9 14 ldy #$AA ; A0 AA inx ; E8 ; XMIT 1 BYTE "29" THIS IS jsr FSL ; 20 61 10 CRC2 FOR DATA FIELD ALL "00" lda #$92 ; A9 92 ldy #$54 ; A0 54 inx ; E8 ; XMIT 1 BYTE "4E" THIS IS jsr FSL ; 20 61 10 1 BYTE OF GAP 3 FIRST HALF lda #$92 ; A9 92 ldx #$17 ; A2 17 XMIT 23 BYTES "4E" THIS jsr FSL ; 20 61 10 COMPLETES FIRST HALF GAP3 ldy SCTPT ; A4 F6 ldx SCTRS,Y ; BE A8 17 stx SCTNO ; 86 FB MOV NXT SCTR IN inc SCTPT ; E6 F6 cpy #$11 ; C0 11 CHK FOR 18 SCTRS FRMTD bne L0F7E ; D0 29 lda #$D3 ; A9 D3 sta SSDA0 ; 8D 00 01 REST XMIT lda WGOFF ; AD 95 01 sta PORTB2 ; 8D 82 02 TURN OFF WG inc TRKNO ; E6 F9 inc SCTTBL+4 ; EE AA 01 jsr EGOFF ; 20 29 12 ldx #$28 ; A2 28 lda DH80T ; AD 99 01 beq L0F72 ; F0 03 jsr XTND3 ; 20 09 08 GO TEST FOR MAX # OF TRKS TO FORMAT L0F72 cpx TRKNO ; E4 F9 CHK FOR ALL TRKS FORMATED beq L0F81 ; F0 0B ldx #$80 ; A2 80 jsr STEP ; 20 88 10 jmp L0E56 ; 4C 56 0E GO FORMAT ANOTHR TRK L0F7E jmp L0EBD ; 4C BD 0E ;################################################### ; Format test ;################################################### ; TESTS ALL SCTRS ; AFTR ACTUAL ; FORMAT AND COMPILES LISTING OF ; BAD SCTRS TO SEND TO COLEN AT ; END. (63 BAD SCTRS MAX) ; L0F81 lda #$52 ; A9 52 sta CTLCMD ; 8D 82 01 jsr RDWRLT ; 20 70 11 ldx #$00 ; A2 00 stx BFRPNT ; 8E E1 01 ldy #$80 ; A0 80 L0F90 lda SCTRS,X ; BD A8 17 sta $0000,Y ; 99 00 00 iny ; C8 inx ; E8 inx ; E8 cpx #$12 ; E0 12 bne L0FA1 ; D0 04 ldx #$01 ; A2 01 stx ZP91 ; 86 91 L0FA1 cpx #$11 ; E0 11 bne L0F90 ; D0 EB dec SCTTBL+4 ; CE AA 01 L0FA8 ldx #$80 ; A2 80 L0FAA lda ZPRL,X ; B5 00 inx ; E8 stx FSCTBP ; 8E E0 01 sta SCTTBL+6 ; 8D AC 01 jsr STSUP1 ; 20 56 12 DO CRC ON SCTR ID FIELD lda #$60 ; A9 60 sta ABLE ; 8D 97 01 lda #$B1 ; A9 B1 sta BAKER ; 8D 96 01 lda #$01 ; A9 01 jsr ORINMD ; 20 73 15 jsr L0BDF ; 20 DF 0B dec INMODE ; CE DC 01 bcs L0FF2 ; B0 25 L0FCD ldx FSCTBP ; AE E0 01 cpx #$92 ; E0 92 bne L0FAA ; D0 D6 ldy SCTTBL+4 ; AC AA 01 bne L0FE4 ; D0 0B lda DH80T ; AD 99 01 beq L103D ; F0 5F BRANCH IF NOT DH OR 96 TPI DRVS jsr XTND5 ; 20 0F 08 jmp L103D ; 4C 3D 10 L0FE4 dey ; 88 sty SCTTBL+4 ; 8C AA 01 ldx #$00 ; A2 00 ldy #$01 ; A0 01 jsr STPTST ; 20 5E 17 STP TO NXT TRK jmp L0FA8 ; 4C A8 0F CONT TST L0FF2 lda #$08 ; A9 08 jsr ORINST ; 20 34 15 SET FORMAT ERR BIT INSTAT ; ; TRACK/SECTOR CONVERSION TO ; 2 BYTE SECTOR NUMBER ; ldy #$00 ; A0 00 sty MSBSB ; 8C E4 01 ldx BFRPNT ; AE E1 01 lda SCTTBL+4 ; AD AA 01 GET TRK NMBR asl A ; 0A sta TMPSB ; 8D E3 01 SAVE TIMES TWO asl A ; 0A rol MSBSB ; 2E E4 01 asl A ; 0A rol MSBSB ; 2E E4 01 asl A ; 0A rol MSBSB ; 2E E4 01 adc TMPSB ; 6D E3 01 tay ; A8 lda #$00 ; A9 00 adc MSBSB ; 6D E4 01 sta MSBSB ; 8D E4 01 tya ; 98 clc ; 18 adc SCTTBL+6 ; 6D AC 01 sta ZPRL,X ; 95 00 lda #$00 ; A9 00 adc MSBSB ; 6D E4 01 inx ; E8 sta ZPRL,X ; 95 00 lda DH80T ; AD 99 01 beq L1035 ; F0 03 jsr XTND11 ; 20 21 08 GOTO INCREASE SEC # FOR SIDE 2 L1035 inx ; E8 stx BFRPNT ; 8E E1 01 cpx #$7E ; E0 7E bne L0FCD ; D0 90 BRNCH IF BAD SCTR BUFR NOT FULL L103D lda #$FF ; A9 FF ldx BFRPNT ; AE E1 01 sta ZPRL,X ; 95 00 inx ; E8 sta ZPRL,X ; 95 00 sta SCTTBL+4 ; 8D AA 01 lda #$21 ; A9 21 sta CTLCMD ; 8D 82 01 lda INSTAT ; AD DD 01 and #$08 ; 29 08 bne L1059 ; D0 03 BRNCH IF ANY BAD SCTRS jmp L0CEE ; 4C EE 0C L1059 lda #$F7 ; A9 F7 jsr ANINS ; 20 6C 15 CLR 105B. curts code ends here jmp L0D11 ; 4C 11 0D FSL bit SSDA0 ; 2C 00 01 bvc FSL ; 50 FB sta SSDA1 ; 8D 01 01 sty SSDA1 ; 8C 01 01 dex ; CA bne FSL ; D0 F2 rts ; 60 ;###################################################### ; Motor on delay. command U ;###################################################### MOTRON jsr SAA ; 20 7B 17 SEND ACK jsr SPMON ; 20 75 13 ldx #$FF ; A2 FF bit INMODE ; 2C DC 01 bvc L1082 ; 50 05 stx SPMSDC ; 8E EB 01 bvs L1085 ; 70 03 L1082 stx SPSDC2 ; 8E A2 01 L1085 jmp L0DC0 ; 4C C0 0D ;###################################################### ; step ;###################################################### STEP bit INMODE ; 2C DC 01 bvc L10C6 ; 50 39 STEP1 lda #$A0 ; A9 A0 sta TIMR3 ; 8D 9E 03 lda PORTB1 ; AD 82 03 and #$3C ; 29 3C inx ; E8 bmi L10AC ; 30 12 dec PRSTRK ; CE CE 01 lsr A ; 4A sta STPSCR ; 8D CD 01 and #$02 ; 29 02 beq L10BE ; F0 19 lda #$20 ; A9 20 ora STPSCR ; 0D CD 01 bpl L10C1 ; 10 15 L10AC inc PRSTRK ; EE CE 01 asl A ; 0A sta STPSCR ; 8D CD 01 and #$40 ; 29 40 beq L10BE ; F0 07 lda #$04 ; A9 04 ora STPSCR ; 0D CD 01 bpl L10C1 ; 10 03 L10BE lda STPSCR ; AD CD 01 L10C1 sta PORTB1 ; 8D 82 03 dey ; 88 rts ; 60 ; L10C6 lda #$A0 ; A9 A0 sta TIMR3 ; 8D 9E 03 lda PORTB3 ; AD 02 02 and #$3C ; 29 3C inx ; E8 bmi L10E5 ; 30 12 dec PRTRK2 ; CE A1 01 lsr A ; 4A sta STPSCR ; 8D CD 01 and #$02 ; 29 02 beq L10F7 ; F0 19 lda #$20 ; A9 20 ora STPSCR ; 0D CD 01 bpl L10FA ; 10 15 L10E5 inc PRTRK2 ; EE A1 01 asl A ; 0A sta STPSCR ; 8D CD 01 and #$40 ; 29 40 beq L10F7 ; F0 07 lda #$04 ; A9 04 ora STPSCR ; 0D CD 01 bpl L10FA ; 10 03 L10F7 lda STPSCR ; AD CD 01 L10FA sta PORTB3 ; 8D 02 02 dey ; 88 rts ; 60 ;############################################### L10FF ldx #$00 ; A2 00 cpx SCTTBL+4 ; EC AA 01 clc ; 18 bne L1111 ; D0 0A lda SCTTBL+5 ; AD AB 01 bne L1111 ; D0 05 lda #$03 ; A9 03 cmp SCTTBL+6 ; CD AC 01 L1111 rts ; 60 ;############################################### MFUTST bit INMODE ; 2C DC 01 bvc SPM2FU ; 50 0E SPMFU lda PORTA1 ; AD 80 03 lsr A ; 4A lsr A ; 4A lda #$10 ; A9 10 bcs L1122 ; B0 02 lda #$00 ; A9 00 L1122 jmp ORSTF ; 4C 2D 15 ; SPM2FU lda PORTA3 ; AD 00 02 lsr A ; 4A lsr A ; 4A lda #$10 ; A9 10 bcs L1130 ; B0 02 lda #$00 ; A9 00 L1130 jmp ORSTF2 ; 4C 45 15 ;############################################## ; REPOSITION HEAD ;############################################## ERRTRY dex ; CA stx PACNTR ; 8E D4 01 tya ; 98 bne L1145 ; D0 0B cpx #$02 ; E0 02 bne L1145 ; D0 07 ldy #$2C ; A0 2C jsr REHME ; 20 FE 12 bmi L1162 ; 30 1D L1145 cpx #$01 ; E0 01 bne L1165 ; D0 1C ldy STPDIR ; AC 9D 01 bmi L1159 ; 30 0B dec TRKNBR ; CE DA 01 jsr L1166 ; 20 66 11 inc TRKNBR ; EE DA 01 bpl L1162 ; 10 09 L1159 inc TRKNBR ; EE DA 01 jsr L1166 ; 20 66 11 dec TRKNBR ; CE DA 01 L1162 jsr L1166 ; 20 66 11 L1165 rts ; 60 L1166 lda TRKNBR ; AD DA 01 jsr CSTEP ; 20 3E 17 jsr STPTST ; 20 5E 17 rts ; 60 ;################################################# RDWRLT lda INMODE ; AD DC 01 asl A ; 0A bpl L1199 ; 10 23 ldx #$1A ; A2 1A asl A ; 0A bmi L117D ; 30 02 ldx #$19 ; A2 19 L117D stx PORTA2 ; 8E 80 02 lda PORTA3 ; AD 00 02 and #$E7 ; 29 E7 sta PORTA3 ; 8D 00 02 ldx CTLCMD ; AE 82 01 cpx #$52 ; E0 52 beq L1195 ; F0 06 ora #$10 ; 09 10 L1191 sta PORTA3 ; 8D 00 02 rts ; 60 L1195 ora #$08 ; 09 08 bne L1191 ; D0 F8 L1199 ldx #$53 ; A2 53 asl A ; 0A bmi L11A0 ; 30 02 ldx #$4B ; A2 4B L11A0 txa ; 8A ldx CTLCMD ; AE 82 01 cpx #$52 ; E0 52 beq L11AB ; F0 03 clc ; 18 adc #$40 ; 69 40 L11AB sta PORTA2 ; 8D 80 02 rts ; 60 ;############################################## L11AF lda PORTB1 ; AD 82 03 bpl L11AF ; 10 FB bmi L11BD ; 30 07 CINPUT bit PORTB1 ; 2C 82 03 bvc L120C ; 50 51 bpl CINPUT ; 10 F9 L11BD lda INMODE ; AD DC 01 and #$81 ; 29 81 cmp #$01 ; C9 01 beq L11ED ; F0 27 ldy #$0B ; A0 0B L11C8 dey ; 88 bne L11C8 ; D0 FD ldy #$78 ; A0 78 L11CD tya ; 98 ldy #$0E ; A0 0E L11D0 dey ; 88 bne L11D0 ; D0 FD tay ; A8 lda PORTB1 ; AD 82 03 rol A ; 2A ror UNITNB,X ; 7E 81 01 iny ; C8 bpl L11F4 ; 10 16 lda UNITNB,X ; BD 81 01 eor #$FF ; 49 FF sta UNITNB,X ; 9D 81 01 inx ; E8 cpx INSCRT ; EC DE 01 bne L1205 ; D0 19 rts ; 60 L11ED ldy #$78 ; A0 78 nop ; EA ldy #$09 ; A0 09 bne L11D0 ; D0 DC L11F4 lda INMODE ; AD DC 01 and #$81 ; 29 81 cmp #$01 ; C9 01 bne L11CD ; D0 D0 tya ; 98 ldy #$02 ; A0 02 nop ; EA nop ; EA nop ; EA bne L11D0 ; D0 CB L1205 ldy #$0D ; A0 0D L1207 dey ; 88 bne L1207 ; D0 FD beq CINPUT ; F0 AA L120C jmp CMD2 ; 4C 9A 0A ;############################################## CRCSUP lda #$01 ; A9 01 jsr ORINMD ; 20 73 15 ldx #$00 ; A2 00 ldy #$E2 ; A0 E2 sty BAKER ; 8C 96 01 ldy #$95 ; A0 95 sty ABLE ; 8C 97 01 jsr L1403 ; 20 03 14 lda #$FE ; A9 FE jsr ANDNMD ; 20 7A 15 rts ; 60 ;############################################## EGOFF lda #$1A ; A9 1A sta TIMR3 ; 8D 9E 03 L122E lda TIM1R ; AD 95 03 bpl L122E ; 10 FB lda #$FF ; A9 FF sta PORTB2 ; 8D 82 02 rts ; 60 ;################################################# SETSUP jsr SAA ; 20 7B 17 SEND ACK jsr SPMON ; 20 75 13 jsr RDWRLT ; 20 70 11 lda #$03 ; A9 03 sta PACNTR ; 8D D4 01 jsr L16F6 ; 20 F6 16 lda SCTNBR ; AD DB 01 sta SCTTBL+6 ; 8D AC 01 lda TRKNBR ; AD DA 01 sta SCTTBL+4 ; 8D AA 01 STSUP1 ldx #$F8 ; A2 F8 DO CRC ON SCTR ID FIELD jsr CRCGEN ; 20 FB 13 ldx BAKER ; AE 96 01 stx SCTTBL+8 ; 8E AE 01 sta SCTTBL+9 ; 8D AF 01 STSUP2 lda PORTB3 ; AD 02 02 ldx SCTTBL+4 ; AE AA 01 cpx #$14 ; E0 14 bit DH80T ; 2C 99 01 bvc L1274 ; 50 03 jsr XTND13 ; 20 27 08 L1274 bcc L127A ; 90 04 and #$FE ; 29 FE bne L127C ; D0 02 L127A ora #$01 ; 09 01 L127C sta PORTB3 ; 8D 02 02 lda TRKNBR ; AD DA 01 jsr CSTEP ; 20 3E 17 rts ; 60 ;########################################################## ; Buffer out? ;########################################################## BFROUT jsr L10FF ; 20 FF 10 stx CSSCRT ; 8E E5 01 bcc L129C ; 90 0E lda #$21 ; A9 21 cmp CTLCMD ; CD 82 01 beq L129C ; F0 07 L1295 lda ZPRL,X ; B5 00 sta ZP80,X ; 95 80 inx ; E8 bpl L1295 ; 10 F9 L129C clc ; 18 bit INMODE ; 2C DC 01 bmi L12A5 ; 30 03 jmp XTND9 ; 4C 1B 08 L12A5 php ; 08 jsr OUTPUT ; 20 42 13 ldy #$08 ; A0 08 L12AB dey ; 88 bne L12AB ; D0 FD L12AE ldy #$08 ; A0 08 L12B0 dey ; 88 bne L12B0 ; D0 FD ldy ZPRL,X ; B4 00 sty TMPOUT ; 8C 86 01 jsr OUTPUT ; 20 42 13 plp ; 28 jsr L15D0 ; 20 D0 15 php ; 08 inx ; E8 bne L12AE ; D0 EB lda CSSCRT ; AD E5 01 plp ; 28 adc #$00 ; 69 00 sta TMPOUT ; 8D 86 01 ldy #$07 ; A0 07 L12CE dey ; 88 bne L12CE ; D0 FD jsr OUTPUT ; 20 42 13 ;#################################################### ; Close output port ;#################################################### RSTOUT ldx PBDDR1 ; AE 83 03 dex ; CA stx PBDDR1 ; 8E 83 03 rts ; 60 ;#################################################### WSL bit SSDA0 ; 2C 00 01 bvc WSL ; 50 FB lda ZPRL,X ; B5 00 ror A ; 6A lsr A ; 4A lsr A ; 4A lsr A ; 4A tay ; A8 lda CDLT,Y ; B9 B9 17 sta SSDA1 ; 8D 01 01 lda ZPRL,X ; B5 00 and #$1F ; 29 1F tay ; A8 lsr A ; 4A lda CDLT,Y ; B9 B9 17 sta SSDA1 ; 8D 01 01 inx ; E8 bne WSL ; D0 DF rts ; 60 ;#################################################### REHME ldx #$24 ; A2 24 bit DH80T ; 2C 99 01 bvc L1308 ; 50 03 jsr XTND7 ; 20 15 08 unused. what does it do? L1308 bit INMODE ; 2C DC 01 bvs L132E ; 70 21 stx PORTB3 ; 8E 02 02 L1310 jsr STEP ; 20 88 10 beq L1320 ; F0 0B L1315 lda TIM1R ; AD 95 03 bpl L1315 ; 10 FB jmp L1310 ; 4C 10 13 ; jmp L132E ; 4C 2E 13 how does it get here? ; L1320 sty PRTRK2 ; 8C A1 01 L1323 lda #$80 ; A9 80 sta TIMR3 ; 8D 9E 03 L1328 lda TIM1R ; AD 95 03+ bpl L1328 ; 10 FB rts ; 60 L132E stx PORTB1 ; 8E 82 03 L1331 jsr STEP ; 20 88 10 beq L133D ; F0 07 L1336 lda TIM1R ; AD 95 03 bpl L1336 ; 10 FB bmi L1331 ; 30 F4 L133D sty PRSTRK ; 8C CE 01 beq L1323 ; F0 E1 ;##################################################### ; send byte sio ;##################################################### OUTPUT lda PORTB1 ; AD 82 03 output and #$FE ; 29 FE sta PORTB1 ; 8D 82 03 start bit ldy ZPRL ; A4 00 ldy #$78 ; A0 78 L134E nop ; EA nop ; EA nop ; EA sty YSAVE ; 8C E6 01 ldy #$0E ; A0 0E L1356 dey ; 88 bne L1356 ; D0 FD ldy YSAVE ; AC E6 01 lsr A ; 4A ror TMPOUT ; 6E 86 01 rol A ; 2A sta PORTB1 ; 8D 82 03 iny ; C8 bpl L134E ; 10 E7 lsr A ; 4A sec ; 38 rol A ; 2A ldy #$11 ; A0 11 L136C dey ; 88 bne L136C ; D0 FD nop ; EA nop ; EA sta PORTB1 ; 8D 82 03 rts ; 60 ;################################################ ; Turn on motor ;################################################ SPMON bit INMODE ; 2C DC 01 +*drive 1 or 2? bvc L1396 ; 50 1C lda PORTA1 ; AD 80 03 lsr A ; 4A lsr A ; 4A bcs L1390 ; B0 0F lda #$6A ; A9 6A sta PORTA1 ; 8D 80 03 lda #$FF ; A9 FF sta TIMR2 ; 8D 9F 03 lda #$04 ; A9 04 sta SPMDLC ; 8D B1 01 L1390 lda #$18 ; A9 18 sta SPMSDC ; 8D EB 01 rts ; 60 ; L1396 lda PORTA3 ; AD 00 02 lsr A ; 4A lsr A ; 4A bcs L13AC ; B0 0F lda #$02 ; A9 02 sta PORTA3 ; 8D 00 02 lda #$FF ; A9 FF sta TIMR23 ; 8D 1F 02 lda #$04 ; A9 04 sta SPMDC2 ; 8D A3 01 L13AC lda #$18 ; A9 18 sta SPSDC2 ; 8D A2 01 rts ; 60 ;################################################# SPMDY bit INMODE ; 2C DC 01 bvc L13DC ; 50 25 lda INSTAT ; AD DD 01 lsr A ; 4A lsr A ; 4A lsr A ; 4A bcc L13D6 ; 90 17 L13BF lda TIM1R ; AD 95 03 bpl L13BF ; 10 FB dec SPMDLC ; CE B1 01 beq L13D1 ; F0 08 lda #$FF ; A9 FF sta TIMR2 ; 8D 9F 03 jmp L13BF ; 4C BF 13 L13D1 lda #$FB ; A9 FB jsr ANINS ; 20 6C 15 L13D6 lda #$10 ; A9 10 jsr L1523 ; 20 23 15 rts ; 60 ; L13DC lda INMODE ; AD DC 01 and #$04 ; 29 04 beq L13FA ; F0 17 L13E3 lda TIMR3R ; AD 15 02 bpl L13E3 ; 10 FB dec SPMDC2 ; CE A3 01 beq L13F5 ; F0 08 lda #$FF ; A9 FF sta TIMR23 ; 8D 1F 02 jmp L13E3 ; 4C E3 13 L13F5 lda #$FB ; A9 FB jsr ANDNMD ; 20 7A 15 L13FA rts ; 60 ;#################################################### ; Generate CRC ;#################################################### CRCGEN lda #$FF ; A9 FF sta ABLE ; 8D 97 01 sta BAKER ; 8D 96 01 L1403 lda INMODE ; AD DC 01 lsr A ; 4A .BYTE $BD,$AE,$00 ;lda ZPCRC,X ABSOLUTE,X. not zeropage,X ; Error in assembler? bcc L140E ; 90 02 lda ZPRL,X ; B5 00 L140E eor BAKER ; 4D 96 01 sta SCRT1 ; 8D A4 01 lsr A ; 4A lsr A ; 4A lsr A ; 4A lsr A ; 4A eor BAKER ; 4D 96 01 tay ; A8 lda INMODE ; AD DC 01 lsr A ; 4A tya ; 98 bcc L145C ; 90 39 eor ZPRL,X ; 55 00 L1425 and #$0F ; 29 0F sta SCRT2 ; 8D A5 01 lda SCRT1 ; AD A4 01 and #$F0 ; 29 F0 eor SCRT2 ; 4D A5 01 sta SCRT2 ; 8D A5 01 lsr A ; 4A lsr A ; 4A lsr A ; 4A eor ABLE ; 4D 97 01 sta ABLE ; 8D 97 01 lda SCRT2 ; AD A5 01 asl A ; 0A asl A ; 0A asl A ; 0A asl A ; 0A sta SCRT1 ; 8D A4 01 eor ABLE ; 4D 97 01 sta BAKER ; 8D 96 01 lda SCRT1 ; AD A4 01 asl A ; 0A eor SCRT2 ; 4D A5 01 sta ABLE ; 8D 97 01 inx ; E8 bne L1403 ; D0 A8 rts ; 60 L145C .BYTE $5D,$AE,$00 ;EOR ZPCRC,X ABSOLUTE,X not zero page,X ; as above jmp L1425 ; 4C 25 14 L1462 jmp L1508 ; 4C 08 15 ;################################################## ; SYNC ;################################################## SYNC lda #$06 ; A9 06 sta SPMDC2 ; 8D A3 01 L146A dec SPMDC2 ; CE A3 01 beq L1462 ; F0 F3 cpy #$01 ; C0 01 beq L1462 ; F0 EF lda #$FF ; A9 FF SYNC01 sta TIMR23 ; 8D 1F 02 L1478 lda TIMR3R ; AD 15 02 bmi L146A ; 30 ED lda #$D0 ; A9 D0 sta SSDA0 ; 8D 00 01 lda #$9B ; A9 9B sta SSDA1 ; 8D 01 01 lda #$D1 ; A9 D1 sta SSDA0 ; 8D 00 01 lda #$44 ; A9 44 sta SSDA1 ; 8D 01 01 lda PORTA1 ; AD 80 03 and #$BF ; 29 BF sta PORTA1 ; 8D 80 03 ora #$40 ; 09 40 sta PORTA1 ; 8D 80 03 lda #$41 ; A9 41 sta SSDA0 ; 8D 00 01 L14A3 lda TIMR3R ; AD 15 02 bmi L146A ; 30 C2 bit PORTA1 ; 2C 80 03 bpl L14A3 ; 10 F6 lda #$89 ; A9 89 sta SSDA1 ; 8D 01 01 ldx #$04 ; A2 04 L14B4 dex ; CA bne L14B4 ; D0 FD bit PORTA1 ; 2C 80 03 bmi L1478 ; 30 BC lda #$40 ; A9 40 sta SSDA0 ; 8D 00 01 lda #$DB ; A9 DB sta SSDA1 ; 8D 01 01 cpy #$02 ; C0 02 beq L1506 ; F0 3C ldx #$02 ; A2 02 lda #$03 ; A9 03 sta TIMR3 ; 8D 9E 03 L14D1 bit TIM1R ; 2C 95 03 bmi L1478 ; 30 A2 bit SSDA0 ; 2C 00 01 bpl L14D1 ; 10 F6 L14DB lda SSDA1 ; AD 01 01 cmp #$A1 ; C9 A1 bne L1478 ; D0 96 dex ; CA bne L14DB ; D0 F6 tya ; 98 bne L1506 ; D0 1E ldx #$78 ; A2 78 L14EA bit SSDA0 ; 2C 00 01 bpl L14EA ; 10 FB lda SSDA1 ; AD 01 01 cmp L0131,X ; DD 31 01 bne L1478 ; D0 81 inx ; E8 lda SSDA1 ; AD 01 01 cmp L0131,X ; DD 31 01 beq L1503 ; F0 03 jmp L1478 ; 4C 78 14 L1503 inx ; E8 bpl L14EA ; 10 E4 L1506 lda #$01 ; A9 01 L1508 rts ; 60 ;################################################## ; how does it get here? ;################################################## lda #$08 ; A9 08 $1509 jsr TIMER ; 20 12 15 jsr STEP ; 20 88 10 rts ; 60 ;################################################## TIMER sta TMRSCR ; 8D DF 01 L1515 dey ; 88 bne L1515 ; D0 FD dec TMRSCR ; CE DF 01 bne L1515 ; D0 F8 rts ; 60 ;###################################################### ; Update status bits ;###################################################### OR0STX bit INMODE ; 2C DC 01 bvc L153B ; 50 18 L1523 pha ; 48 lda #$E8 ; A9 E8 and STFLGS ; 2D D0 01 sta STFLGS ; 8D D0 01 pla ; 68 ORSTF ora STFLGS ; 0D D0 01 sta STFLGS ; 8D D0 01 rts ; 60 ;################################################## ORINST ora INSTAT ; 0D DD 01 sta INSTAT ; 8D DD 01 rts ; 60 ;################################################## L153B pha ; 48 lda #$E8 ; A9 E8 and STFLG2 ; 2D 90 01 sta STFLG2 ; 8D 90 01 pla ; 68 ORSTF2 ora STFLG2 ; 0D 90 01 sta STFLG2 ; 8D 90 01 rts ; 60 ;################################################# CLRST lda #$E8 ; A9 E8 CLRST1 and STFLGS ; 2D D0 01 sta STFLGS ; 8D D0 01 rts ; 60 ;################################################# CLRST2 lda #$E8 ; A9 E8 CLRS12 and STFLG2 ; 2D 90 01 sta STFLG2 ; 8D 90 01 rts ; 60 ;################################################# WPTST lda PORTA1 ; AD 80 03 bit INMODE ; 2C DC 01 bvc L1569 ; 50 03 and #$10 ; 29 10 rts ; 60 L1569 and #$01 ; 29 01 rts ; 60 ;############################################### ANINS and INSTAT ; 2D DD 01 sta INSTAT ; 8D DD 01 rts ; 60 ;############################################### ORINMD ora INMODE ; 0D DC 01 sta INMODE ; 8D DC 01 rts ; 60 ;############################################### ANDNMD and INMODE ; 2D DC 01 sta INMODE ; 8D DC 01 rts ; 60 ;############################################### ORST1 bit INMODE ; 2C DC 01 bvc L158D ; 50 07 ora DEVSTA ; 0D D1 01 sta DEVSTA ; 8D D1 01 rts ; 60 L158D ora DEVST2 ; 0D 91 01 sta DEVST2 ; 8D 91 01 rts ; 60 ;############################################### ANDST1 bit INMODE ; 2C DC 01 bvc L15A0 ; 50 07 and DEVSTA ; 2D D1 01 sta DEVSTA ; 8D D1 01 rts ; 60 L15A0 and DEVST2 ; 2D 91 01 sta DEVST2 ; 8D 91 01 rts ; 60 ;################################################### ; test for valid sector number ;################################################### TSN ldx AUX2 ; AE 84 01 lda AUX1 ; AD 83 01 beq L15B9 ; F0 0A L15AF cpx #$03 ; E0 03 bcs L15BD ; B0 0A cmp #$D1 ; C9 D1 bcs L15C9 ; B0 12 L15B7 clc ; 18 rts ; 60 L15B9 cpx #$00 ; E0 00 bne L15AF ; D0 F2 L15BD sec ; 38 lda DH80T ; AD 99 01 and #$C0 ; 29 C0 beq L15C8 ; F0 03 jsr XTND6 ; 20 12 08 L15C8 rts ; 60 L15C9 cpx #$02 ; E0 02 beq L15BD ; F0 F0 jmp L15B7 ; 4C B7 15 L15D0 lda CSSCRT ; AD E5 01 adc ZPRL,X ; 75 00 sta CSSCRT ; 8D E5 01 rts ; 60 ;################################################# ; Caculate chksum ;################################################# CDCKSM lda #$00 ; A9 00 clc ; 18 L15DC adc UNITNB,X ; 7D 81 01 php ; 08 inx ; E8 cpx INSCRT ; EC DE 01 beq L15EA ; F0 04 plp ; 28 jmp L15DC ; 4C DC 15 L15EA plp ; 28 adc #$00 ; 69 00 cmp UNITNB,X ; DD 81 01 rts ; 60 ;################################################# FWSL lda PORTA2 ; AD 80 02 ora #$1B ; 09 1B nop ; EA nop ; EA nop ; EA lda INMODE ; AD DC 01 asl A ; 0A bmi L1611 ; 30 12 asl A ; 0A asl A ; 0A lda #$EF ; A9 EF ldx #$CF ; A2 CF ldy #$DF ; A0 DF bcs L1621 ; B0 18 lda #$BF ; A9 BF ldx #$3F ; A2 3F ldy #$7F ; A0 7F bcc L1621 ; 90 10 L1611 asl A ; 0A asl A ; 0A lda #$FE ; A9 FE ldx #$FC ; A2 FC ldy #$FD ; A0 FD bcs L1621 ; B0 06 lda #$FB ; A9 FB ldx #$F3 ; A2 F3 ldy #$F7 ; A0 F7 L1621 stx EGON ; 8E 94 01 sty WGOFF ; 8C 95 01 sta PORTB2 ; 8D 82 02 lda #$D3 ; A9 D3 sta SSDA0 ; 8D 00 01 lda #$92 ; A9 92 ldy #$54 ; A0 54 sta SSDA1 ; 8D 01 01 sty SSDA1 ; 8C 01 01 ldx #$93 ; A2 93 stx SSDA0 ; 8E 00 01 rts ; 60 ;################################################ FWSL1 lda #$AA ; A9 AA tay ; A8 ldx #$0C ; A2 0C jsr FSL ; 20 61 10 lda #$44 ; A9 44 ldy #$89 ; A0 89 ldx #$03 ; A2 03 jsr FSL ; 20 61 10 lda #$55 ; A9 55 ldy #$45 ; A0 45 inx ; E8 jsr FSL ; 20 61 10 rts ; 60 ;################################################# INPUT jsr L10FF ; 20 FF 10 stx CSSCRT ; 8E E5 01 bcc L1663 ; 90 02; L1661 ldx #$80 ; A2 80 L1663 lda #$FF ; A9 FF sta TIMR22 ; 8D 9F 02 ldy #$07 ; A0 07 sty INSCRT ; 8C DE 01 inc INMODE ; EE DC 01 clc ; 18 bit INMODE ; 2C DC 01 bmi L1679 ; 30 03 jmp XTND8 ; 4C 18 08 unused data field input ,38k baud L1679 php ; 08 L167A lda TIMR2R ; AD 95 02 bmi L16EF ; 30 70 L167F lda PORTB1 ; AD 82 03 bpl L167A ; 10 F6 ldy #$0C ; A0 0C L1686 dey ; 88 bne L1686 ; D0 FD ldy #$78 ; A0 78 L168B tya ; 98 ldy #$0F ; A0 0F L168E dey ; 88 bne L168E ; D0 FD tay ; A8 lda PORTB1 ; AD 82 03 rol A ; 2A ror ZPRL,X ; 76 00 iny ; C8 bpl L16E0 ; 10 45 lda ZPRL,X ; B5 00 eor #$FF ; 49 FF sta ZPRL,X ; 95 00 plp ; 28 jsr L15D0 ; 20 D0 15 php ; 08 inx ; E8 bne L16E5 ; D0 3C ldx #$04 ; A2 04 L16AB dex ; CA bne L16AB ; D0 FD ldx #$06 ; A2 06 jsr L11AF ; 20 AF 11 sta DICKSM ; 8D 87 01 jsr L10FF ; 20 FF 10 bcc L16C2 ; 90 07 L16BB lda ZP80,X ; B5 80 sta ZPRL,X ; 95 00 inx ; E8 bpl L16BB ; 10 F9 L16C2 lda CSSCRT ; AD E5 01 plp ; 28 adc #$00 ; 69 00 dec INMODE ; CE DC 01 cmp DICKSM ; CD 87 01 php ; 08 ldy #$5A ; A0 5A L16D1 dey ; 88 bne L16D1 ; D0 FD plp ; 28 beq L16DF ; F0 08 lda #$4E ; A9 4E jsr SAA2 ; 20 82 17 jmp L0AF8 ; 4C F8 0A L16DF rts ; 60 L16E0 lda INMODE ; AD DC 01 bmi L168B ; 30 A6 L16E5 ldy #$06 ; A0 06 sty TIMR22 ; 8C 9F 02 L16EA dey ; 88 bne L16EA ; D0 FD beq L167F ; F0 90 L16EF dec INMODE ; CE DC 01 plp ; 28 lda #$FF ; A9 FF rts ; 60 ;################################################### L16F6 lda AUX2 ; AD 84 01 sta SSCTMS ; 8D D7 01 lda AUX1 ; AD 83 01 sta SSCTLS ; 8D D8 01 ldx #$04 ; A2 04 L1704 ror AUX2 ; 6E 84 01 ror A ; 6A dex ; CA bne L1704 ; D0 F9 ror AUX2 ; 6E 84 01 ldx #$04 ; A2 04 L1710 lsr AUX2 ; 4E 84 01 dex ; CA bne L1710 ; D0 FA L1716 asl A ; 0A cmp AUX2 ; CD 84 01 bcs L172E ; B0 12 sta AUX1 ; 8D 83 01 lsr A ; 4A sta TRKNBR ; 8D DA 01 sec ; 38 lda AUX2 ; AD 84 01 sbc AUX1 ; ED 83 01 sta SCTNBR ; 8D DB 01 rts ; 60 L172E lsr A ; 4A tax ; AA dex ; CA lda #$10 ; A9 10 clc ; 18 adc AUX2 ; 6D 84 01 sta AUX2 ; 8D 84 01 txa ; 8A jmp L1716 ; 4C 16 17 ;############################################### CSTEP ldx #$80 ; A2 80 ldy #$00 ; A0 00 sec ; 38 bit INMODE ; 2C DC 01 bvs L174E ; 70 06 sbc PRTRK2 ; ED A1 01 jmp L1751 ; 4C 51 17 L174E sbc PRSTRK ; ED CE 01 L1751 beq L175D ; F0 0A bpl L175C ; 10 07 ldx #$00 ; A2 00 eor #$FF ; 49 FF clc ; 18 adc #$01 ; 69 01 L175C tay ; A8 L175D rts ; 60 ;################################################## STPTST beq L177A ; F0 1A L1760 jsr STEP ; 20 88 10 beq L176D ; F0 08 L1765 lda TIM1R ; AD 95 03 bpl L1765 ; 10 FB jmp L1760 ; 4C 60 17 L176D lda #$14 ; A9 14 sta TIMR2 ; 8D 9F 03 L1772 lda TIM1R ; AD 95 03 bpl L1772 ; 10 FB stx STPDIR ; 8E 9D 01 L177A rts ; 60 ;################################################# SAA bit PORTB1 ; 2C 82 03 ssa bvs SAA ; 70 FB SAA1 lda #$41 ; A9 41 ACK SAA2 sta TMPOUT ; 8D 86 01 jsr SETOP ; 20 8F 17 jsr OUTPUT ; 20 42 13 jsr RSTOUT ; 20 D4 12 rts ; 60 ;######################################### ;Open serial out port ;######################################### SETOP ldx PORTB1 ; AE 82 03 stx PORTB1 ; 8E 82 03 ldx PBDDR1 ; AE 83 03 inx ; E8 stx PBDDR1 ; 8E 83 03 rts ; 60 ;####################################################### ; 11 byte id field ;####################################################### IDFLD .byte $A1,$A1,$A1,$FE,$FF,$00,$FF,$01 .byte $FF,$FF,$4E ; sector table. where is sector 1??? SCTRS .byte $0A,$09,$12,$08,$11,$07,$10,$06 .byte $0F,$05,$0E,$04,$0D,$03,$0C,$02 .byte $0B CDLT .byte $AA,$A9,$A4,$A5,$92,$91,$94,$95 .byte $4A,$49,$44,$45,$52,$51,$54,$55 .byte $2A,$29,$24,$25,$12,$11,$14,$15 .byte $4A,$49,$44,$45,$52,$51,$54,$55 L17D9 .byte $04,$D0,$02,$00,$01,$07,$0C,$00 .byte $00,$00,$AA,$55,$00,$00,$00,$00 .byte $00,$00,$00,$00,$00,$00,$00,$00 .byte $00,$00,$00,$00,$00,$00,$00,$00 .byte $00,$00,$00 * = $17FC .word $0800,$0800

Yes please. put me down for one. James

Apart from a106 and a107 loading at wrong addresses (need to be swapped around) they are identical, which is slightly different to what Curt has posted above. James

A preliminary look at the rom shows a few interesting things. The code is almost the same as what curt has provided, tho curts code has been truncated. The rom has an extra command (X). There is no 38k baud code. no rom jump table at 800 tho there are several jumps to the non existent table. A bit on one port is checked before a jump to missing table but as this bit never changes, the jumps never happen. It doesn't have a FDC chip. No idea what encoding is used on the disk. James

I saw a tv program once about this. IBM Approached Microsoft about basic and asked them about an os (dos). microsoft didn't do one. IBM went to to Digital research about CP/M, After lawyers argued about non disclosure agreements and other stupid stuff IBM got jack of this and went back to microsoft and asked them if they could do a OS (dos). Microsoft found and bought a program called quick and dirty dos for some $100,000, did a couple of mods which ibm got as PCdos. latter microsoft released it as MSdos. James

Can you please dump the roms for everyone's curiosity (namely mine ) James

oops. above should read-- must ask an owner......... my bad james

Judging by the code, It is a 68b52 which i think is a type of Asynchronous Communications Interface Adapter from what i am able to find out about the chip which is very little. (ie nothing). Looks like the 815 used the processor to do all the hard work of writing data to the disk , calculating crc etc instead of using a disk controller. Must an owner of an 815 to dump both roms and append it to curts listing. James

Hmm. it appears that some of the code is missing. James

I found that one not long after it came out. I have recently dissembled it to have a look. Quite hard to find what the commands are. The bb must do part of the decoding before passing parms to the FB. James

For the indus track buffering to work, you will need to install indus ram charger board. only a few prototypes where ever made. But someone has made one using static ram chips. search this forum for more info and how to make one. I don't believe sparta dos 4.45 can enable the indus track buffering at this time. However if you can get dosxl with super syncomesh, it will install the track buffering software. There may be a problem with the dosxl version of super syncomesh with spartados. As for version of indus GT, if it can read enhanced density disks beyond sector 720, it is the latest version rom (1.2) Don't believe anyone that says they have version 1.4. It isn't As a side note, with ram charger installed, the indus can become a z80 cpm computer which uses the atari as a consol. A search will also find this. James

is the toms a clone of an indusGT with upgrades?? I must agree that a 1050 with an upgrade is the best drive. James

Always check with a DMM/volt meter polarity of the single line cable. I personally have found that on some, the woven part to be posative. Usually made in china. james OK, I'll do that if you explain to me 1. what is a DMM? 2. how DO I check the polarity? 3. Why should I do this? BTW, it's "positive", NOT "posative". I'm just going skiing now, although it may be a bit difficult in this weather (over 25'C and no snow). 1) DMM = Digital Multi Meter. Handy device for all sorts of things. 2) Every DMM has a red lead and a black lead (ones I have seen) Black is usally in common or ground terminal. Red can go in 1 or more positions depending on the meter. They will show, when measuring volts, a minus sign if red lead is more negative then the black lead. Nothing or a + is shown when red lead is more positive then black lead. Voltage is shown as well by the way. 3) It is always good to check which wire is what before modifying anything. Besides, i was referring to the single lead type that has a center conductor with a Brade type surrounding it. ALWAYS check this type. DONT assume the center conductor is positive. 4) I wrote reply this morning on shitty audiosonic android tablet. It cannot access android market to download any app. Any spelling errors don't show. 5) My spelling isn't the best so dont shoot me for it. James

Always check with a DMM/volt meter polarity of the single line cable. I personally have found that on some, the woven part to be posative. Usually made in china. james

In countries outside of the US, It maybe a different story. Have a couple of old and new of 410's here. all are 6V external. James

Better put your memory in for it's bi annual checkup The 410 is DC. 6V in fact. James

As a matter of fact, it does. I once pulled the code apart and assembled it to work with a different ram config. Also to see the special format command and add it to another 1050 hardware upgrade that I had. Looking tonight at my Harddrive images I have, the source files are damaged. DOHHHHHHHHH!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! James

What the fast load is, is how the sectors are arranged on the disk. Normal single density was something like this 1,3,5,7,9,11,13,15,17,2,4,6,8,10,12,14,16,18 Fast load is 17,15,13,11,9,7,5,3,1,18,16,14,12,10,8,6,4,2. There is a gap between last sector and first sector on each track that is almost a sector in length. In 2nd example, it would be between sectors 2 and 17. Reading the fastload puts the sectors slightly closer together so drive waits a little less time for sector to come up. I did read about it in the archiver manual i think it was. Usd has fastload sector map built in. James

I do remember a program from early eighties that showed an 800 playing space invaders. One of the first shots was a cassette being loaded into a 410 (space invaders?) Thought program was done in england Tho could be wrong. It was more about computers and chips but did show atari. James

I don't know about other countries, but her in oz, the transformers are protected by a thermal fuse under the tape of the primary. I did one once when i shorted the end that plugs into the drive (don't ask) James