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Showing results for tags 'CPU'.
Found 12 results
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It is probably documented somewhere, but I cannot find the answer, so I though I would ask here. It is said that after the NMI line goes low, the CPU cannot accept another NMI until the NMI line goes up and low again. So, assuming that there are glitches on the NMI line, so that after the initial, full pulse the line shortly goes high and then low again (uncontrollably or under external control, no matter), so that there are effectively multiple valid NMI pulses within the span of, say, 20-30 CPU clock cycles, then, after the CPU starts servicing the first NMI pulse of the series, when will be the earliest point (or time), in which it will be able to accept and start servicing another NMI? I.e. immediately after loading the vectors to the PC, or perhaps after the first instruction of the handler?
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Is there interest in the community for a little board, built entirely with general-purpose, currently-manufactured parts, which replaces the 'Sally' custom CPU in the 8-bit systems? Here is a video of the reverse-engineering and design process: https://youtu.be/iTJLFSFqFeE
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Hello there! I recently watched on YouTube a video from RetroManCave (Neil), titled "Inside the BBC Micro - Trash to Treasure (Part 2)" (https://www.youtube.com/watch?v=bQCgzIWZo0o) At 0:03:35, Neil explains that the BBC Micro's 6502 runs at 2 MHz, which makes it pretty fast, compared to other computers from the same period, for instance the Apple II that ran at 1 MHz (1.9 MHz in turbo mode). Of course, I regret that Neil didn't mention Atari's 1.79 (1.77) MHz at that point. Later at 0:08:00, Neil mentions the Rugg/Feldman benchmarks for BASIC, in which Atari BASIC (and the OS FPP) does not help to make the computer shine. To me, it's not really fair to compare the computers with merely their CPU speed (*) and Rugg/Feldman benchmarks for BASIC figures: - The Atari runs MUCH FASTER with other BASIC, such as Turbo BASIC XL, to name just one - The Atari 8-bit architecture, with dedicated additional chips, allows the CPU to focus on the main tasks, whilst the other chips deal with video, sound, P/M, etc. In lots of other computers from the same period, the CPU deals with everything, so a higher clock rate is not enough to make it faster! My question is: How to compare - with justice - the 800XL with the C64, the Apple IIe, the BBC Micro, etc in terms of performance? Any suggestion of bench marking method? (*) Same 6502 CPU for instance; We all know that a 6502 & a Z80 at 2 MHz are NOT equally powerful -
Has anybody documented the undefined behavior of the TMS9900 data and address buses when no memory cycle is happening? I noticed this today while debugging a hardware glitch (unsuccessful so far): During the Add instruction, the databus repeats the two operand values. I don't see this behavior documented in the TMS9900 manual. It seems like a nice feature to have. I guess it's the ALU "leaking" its values onto the data bus. What does an Add instruction do? The sequence of operations is roughly: instruction fetch instruction decode fetch source operand fetch destination operand internal ALU cycle (in this case, ADD) store destination operand Here is an observed sample case where the cpu adds 0010 + dec8 = ded8: My registers: WP 83E0 PC 7d32 (whole program from 7d00 to 7d80) R0 0010 R5 A000 Bus observations (each row is at least 1 clock cycle): ADDR DATA Signals Action 7d32 a540 MEMEN DBIN IAQ read instruction: A R0,*R5 ???? xx40 decode ???? xx10 decode 83e0 xx10 MEMEN DBIN fetch R0 from 83e0 a000 dec8 MEMEN DBIN fetch dec8 from a000 ???? xxc8 internal ???? xx10 internal a000 ded8 MEMEM WE store result to a000 xx are the high byte I can't see (I'm reading the side port. I only see one half of an internal 16 bit bus read.) ?? are addresses I missed cuz I only grab the address when MEMEN is asserted. The internal cycle values xxc8 and xx10 match the destination and source values. I'll be taking more notes on other instructions.
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I recently bought a broken intellivision off of eBay, and after messing around with it i believe that the problem is the CPU. I don't have a working unit, or any other units for that matter. I was hoping i could find a new cpu (preferably a whole board, in case there is any other problems with it) from someone on this form. I really want to try and play some intv games, especially since they are cheap. -
I always considered VCS marvel at engineering but, at the same time, it was always to constraining for me so I settled for less perfect but much more capable Atari 800. Some recently released VCS games seemed to achieve impossible. Quickly I found that some of the games have even more help from the cartridge than what was available back in the day in the form of Display Processor Chip (as used in Pitfall II). In those games it is ARM processor, hidden in Harmony / Melody cartridge, which does the heavy lifting and original CPU (6507) tries hard but can not really keep up. This led me to the following question: Would it make sense to plug in Harmony-like expansion in place of the VCS original CPU?
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Aside from the neat cross-over between classic computers and synths with people like Bil Herd and Bob Yannes, I find it interesting to see how some of our favorite CPUs crop up here and there in the music industry. So I started making a list of synths and samplers that made use of various old-skool CPUs. To start things off, here's a list of what I've been able to find so far. Feel free to correct any errors you might spot: Roland Jupiter 8 Z80 Sequential Circuits Prophet 5 & 10 Z80 Sequential Circuits Prophet 600 Z80 Roland MC4 Z80 Ensoniq EPS-16 68000 E-mu 4060 Z80 Roland MSQ700 Z80 Oberheim OB-8 Z80 MemoryMoog Z80 Emulator I and II Z80 Akai 2700 Z80 E-mu SP-1200 Z80 E-mu Drumulator Z80 Sequential Circuits Drumtraks Z80 Fairlight CMI series II 6800 Fairlight CMI series IIx 6809 Oberheim Xpander 6809 Oberheim Matrix 6809 PPG Wave 2.x 6809 PPG Waverterm A 6809 Ensoniq SDP-1 6809 Ensoniq ESQ1 6809 Ensoniq SQ80 6809 Fairlight CMI series III 68000 and 6809 Quasar M8 6800
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Hello Everyone, I just got a hold of a Darth Vader and am trying to get it into working order again and am having video difficulties. It's a Rev 17 board and I'm currently in the process of putting in sockets as I remove the chips. The pictures attached show what my lovely screen looks like as is. Currently I have a known working RIOT chip in it and a new On/Off switch. The RF cable, Missile Command, joystick and power supply all work fantastically with my Woody, so if you have any suggestions that would be great. I was thinking the TIA chip, but before I start desoldering it, I thought I might get some ideas. Cheers
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While I think that the Lynx is just fine with its 6502 CPU, and understand why it didn't get a Motorola 680, I still wonder: What made Atari and Epyx make the final decision to use the MOS 6502 rather than, say, the Zilog Z80b, Intel 8088, or one from Hudsonsoft? What, other than cost possibly, made the 6502 their pick?
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Wondering if any one on here with knowledge of old chips might know anything about this cpu? I was Striping and old teletype I got at a thrift store for parts. It had a the Intel M80c31f chip and I did a quick google on it. I found some specs and read that it has an 8 bit architecture. I was just curious if any old 8 bit computers used this chip and if it was worth saving for anything?
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Has anyone ever tried to run some of the modern CPU benchmarks (like SPECint and SPECfp) on the classic 8-bit (6502, Z80) and 16-bit (68000, 65816) CPUs? My googling has found nothing. (Only thing I could find was a rating for the 68060.) How hard would it be to set something like that up?
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This is a project idea we were chatting about on ##Atari today. The basic idea is that we make it possible for PBI devices to take over the system bus to perform DMA transfers at up to 1.7 megabytes per second. This is done by hooking into the way that ANTIC stops the CPU with a small riser board, and connecting /HALT and a new /DMA signal to two currently unused pins on the PBI. The device protocol would work like this: when a DMA transfer is desired, the device asserts /DMA. Every cycle that starts with /DMA asserted is a DMA cycle for the device *unless* /HALT was asserted before the cycle began, in which case the device has to relinquish to ANTIC. Devices can use the presence of /HALT at a high level during a read of the device's registers to detect whether DMA is present; if not, devices can fall back to programmed I/O. I whipped up a quick board layout for this; the board is also designed to generate a "clean" phi2 output as well as allowing the use of a W65C02 or W65C816 instead of 6502C. It does not support other 6502s or 65C02s which do not have the /BE input. Thoughts?
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