Atari 1200XL PAL hack

[tjlazah]

I am getting a tricked out 1200XL from Atarimax soon! I wanna add a PAL Antic, which one do I need and what else needs to be done? It will have the 32-in-1 OS in it. (B&C lists two Antics one for XL/XE and one for 800/old XL, is that what the 1200XL needs?)

Edited August 30, 2007 by tjlazah

[Marius]

I am getting a tricked out 1200XL from Atarimax soon! I wanna add a PAL Antic, which one do I need and what else needs to be done? It will have the 32-in-1 OS in it. (B&C lists two Antics one for XL/XE and one for 800/old XL, is that what the 1200XL needs?)

 

That is a simple question, with a hard answer.

 

I know Ernest Schreurs has tried to transform his 1200XL ntsc into a PAL machine, but as far as I know it never worked 100%.

 

I guess you also have to replace at least crystall.

 

Perhaps someone knows e-mail address of Ernest Schreurs, or perhaps he is reading this himself. He knows more, that's for sure

 

Marius

[mimo]

Quote from Gunstar.

Good point to bring up. The PAL ANTIC mod will only work in the sense that it will allow most PAL software to run on it on an NTSC computer, while still allowing NTSC software to work too, still needing a TV/monitor that can handle the 50hz refresh instead of 60hz. The 1200's power is still wrong for the UK, though a new powerpack can handle that, but getting it to work on an actual PAL TV/monitor is something different entirely. If your using a monitor like a Commodore 1084 that's rated for 50/60hz then you should be alright though, with just changing out U.S. powerpack for an English/Euro pack. To change it completely over to PAL would require replacement of the NTSC GTIA and OS too, with PAL ones, and a change of crystal so the system runs at the appropriate PAL speed, and that may even require replacement of the 6502 CPU too, but I'm not sure, and maybe some various other changes that I forgot to mention (considering I've never actually turned an NTSC machine into a PAL).
The PAL Antic "upgrade" was only ever meant so that NTSC computers could run most of the PAL software in the U.S. and even then it still requires us NTSC users to get a monitor or TV that can handle the 50hz PAL ANTIC refresh rate, like my 1084S monitor. I still can't hook my 1200XL with it's PAL Antic up to my normal NTSC TV, the horizontal hold just rolls uncontrollably. Some more modern TV's can handle it, mine can't.

[sup8pdct]

Quote from Gunstar.

Good point to bring up. The PAL ANTIC mod will only work in the sense that it will allow most PAL software to run on it on an NTSC computer, while still allowing NTSC software to work too, still needing a TV/monitor that can handle the 50hz refresh instead of 60hz. The 1200's power is still wrong for the UK, though a new powerpack can handle that, but getting it to work on an actual PAL TV/monitor is something different entirely. If your using a monitor like a Commodore 1084 that's rated for 50/60hz then you should be alright though, with just changing out U.S. powerpack for an English/Euro pack. To change it completely over to PAL would require replacement of the NTSC GTIA and OS too, with PAL ones, and a change of crystal so the system runs at the appropriate PAL speed, and that may even require replacement of the 6502 CPU too, but I'm not sure, and maybe some various other changes that I forgot to mention (considering I've never actually turned an NTSC machine into a PAL).
The PAL Antic "upgrade" was only ever meant so that NTSC computers could run most of the PAL software in the U.S. and even then it still requires us NTSC users to get a monitor or TV that can handle the 50hz PAL ANTIC refresh rate, like my 1084S monitor. I still can't hook my 1200XL with it's PAL Antic up to my normal NTSC TV, the horizontal hold just rolls uncontrollably. Some more modern TV's can handle it, mine can't.

 

The difference between the old antic and the new antic as far as I know is the old antic has an 8 bit refresh cycle and the new one has a 9 bit refresh cycle. What it actually means, I am not sure. maybe the new Antic interrupts the 6502 less for memory refresh compared to the old one.

To convert an NTSC machine to PAL, one needs to add a second crystal with a 74LS74 chip and replace the existing one with one slightly faster? or is it slower? In the 1200XL, this will be a chore as there is no provision on the motherboard for the PAL circuitry. Also the modulator will need to be replaced.

 

james

[mimo]

Quote from Gunstar.

Good point to bring up. The PAL ANTIC mod will only work in the sense that it will allow most PAL software to run on it on an NTSC computer, while still allowing NTSC software to work too, still needing a TV/monitor that can handle the 50hz refresh instead of 60hz. The 1200's power is still wrong for the UK, though a new powerpack can handle that, but getting it to work on an actual PAL TV/monitor is something different entirely. If your using a monitor like a Commodore 1084 that's rated for 50/60hz then you should be alright though, with just changing out U.S. powerpack for an English/Euro pack. To change it completely over to PAL would require replacement of the NTSC GTIA and OS too, with PAL ones, and a change of crystal so the system runs at the appropriate PAL speed, and that may even require replacement of the 6502 CPU too, but I'm not sure, and maybe some various other changes that I forgot to mention (considering I've never actually turned an NTSC machine into a PAL).
The PAL Antic "upgrade" was only ever meant so that NTSC computers could run most of the PAL software in the U.S. and even then it still requires us NTSC users to get a monitor or TV that can handle the 50hz PAL ANTIC refresh rate, like my 1084S monitor. I still can't hook my 1200XL with it's PAL Antic up to my normal NTSC TV, the horizontal hold just rolls uncontrollably. Some more modern TV's can handle it, mine can't.

 

The difference between the old antic and the new antic as far as I know is the old antic has an 8 bit refresh cycle and the new one has a 9 bit refresh cycle. What it actually means, I am not sure. maybe the new Antic interrupts the 6502 less for memory refresh compared to the old one.

To convert an NTSC machine to PAL, one needs to add a second crystal with a 74LS74 chip and replace the existing one with one slightly faster? or is it slower? In the 1200XL, this will be a chore as there is no provision on the motherboard for the PAL circuitry. Also the modulator will need to be replaced.

 

james

 

To make the 1200 XL a real PAL machine yes, to make it PAL compatable or an NTSC/PAL highbrid then just adding the Antic works.

[BigBen]

look here http://www.atariage.com/forums/index.php?s...p;#entry1217185

under the picture "Conversion to PAL videosystem, with sep. chroma/luma."

Original board is a 1200XL.

 

BigBen

[Rybags]

9 bit refresh would be to accomodate the greater number of memory rows in 128K systems.

[tjlazer]

I just want to run the occasional PAL demos, not looking to convert the whole machine to PAL. So just a regular XL/XE PAL Antic swap then? Cool.

[walter_J64bit]

When I had the PAL mod running in my 1200XL all I did was the PAL Antic swap I used the A/V cables and Commodore monitor but the monitor is dead now so I'm using a MadCat LCD 7" I had to remove the mod MadCat didn't work with the mod.

[MEtalGuy66]

The difference between the old antic and the new antic as far as I know is the old antic has an 8 bit refresh cycle and the new one has a 9 bit refresh cycle. What it actually means, I am not sure. maybe the new Antic interrupts the 6502 less for memory refresh compared to the old one.

To convert an NTSC machine to PAL, one needs to add a second crystal with a 74LS74 chip and replace the existing one with one slightly faster? or is it slower? In the 1200XL, this will be a chore as there is no provision on the motherboard for the PAL circuitry. Also the modulator will need to be replaced.

 

james

 

The 8bit vs 9bit refresh cycle has nothing to do with the scan rate or system clock. What it does mean is that using "RAS only REFRESH" which is one of two methods supported by most 8-bit DRAMs of the day, the 1200XL ANTIC could only refresh 64k of memory. The later ANTIC used in the 800XL, 65XE, 800XE, XEGS and 130XE machines generated refresh adress "setups" for 256k or (or 9 bits of "ROWS") on the "RAS only refresh" cycle.

 

This is the reason that if you want to upgrade a 1200XL past 64k, you need to either 1) replace the antic with a newer (9-bit refresh) part, or 2)create your own circuit to add the extra bit of "ROW setup" on the refresh cycle. This is the reason that the RAMBO XL has jumper settings for 1200XL...

 

Since the 400, 800 and 1200XL were never sold in Europe, it's probably a safe bet that all PAL ANTIC chips are 9-bit refresh (eg. 800XL, 130XE, etc. which were quite popular in Europe.)

[ijor]

To convert an NTSC machine to PAL, one needs to add a second crystal with a 74LS74 chip and replace the existing one with one slightly faster? or is it slower? In the 1200XL, this will be a chore as there is no provision on the motherboard for the PAL circuitry. Also the modulator will need to be replaced.

To make the 1200 XL a real PAL machine yes, to make it PAL compatable or an NTSC/PAL highbrid then just adding the Antic works.

 

That depends on what you mean by "PAL compatible". If all you want is to have the 50Hz refresh rate, then yes, all you need is to replace the Antic.

 

To be "more" PAL compatible you have to replace GTIA as well though, because GTIA has the "PAL" register. That means that software that adapts the timing at runtime according to the PAL register won't work correctly. But in turn, using a PAL GTIA probably requires replacing the whole video circuitry.

 

To make it 100% PAL compatible computer you need one step further, to replace the main crystal. This might be needed for some very hi-speed third partry drives. This in turn is a whole mess, because you can just replace the crystal, you need the dual one as PAL computers have.

 

Since the 400, 800 and 1200XL were never sold in Europe, it's probably a safe bet that all PAL ANTIC chips are 9-bit refresh (eg. 800XL, 130XE, etc. which were quite popular in Europe.)

 

I think the 400/800 exist in PAL models (they are probably rare, though), only the 1200XL is NTSC only. As a matter of fact B&C does list a PAL 400/800 Antic.

[mimo]

Since the 400, 800 and 1200XL were never sold in Europe, it's probably a safe bet that all PAL ANTIC chips are 9-bit refresh (eg. 800XL, 130XE, etc. which were quite popular in Europe.)

 

The 400/800 were most definately available in Europe, I cut my teeth on a 400 in 1981

[MEtalGuy66]

Since the 400, 800 and 1200XL were never sold in Europe, it's probably a safe bet that all PAL ANTIC chips are 9-bit refresh (eg. 800XL, 130XE, etc. which were quite popular in Europe.)

 

The 400/800 were most definately available in Europe, I cut my teeth on a 400 in 1981

Ok excuse me. They were not sold in Europe in NEARLY the numbers that they were sold in the US.. So I guess its possible that there are PAL versions of the earlier (8-bit refresh) ANTIC as well.

[+warerat]

The difference between the old antic and the new antic as far as I know is the old antic has an 8 bit refresh cycle and the new one has a 9 bit refresh cycle. What it actually means, I am not sure. maybe the new Antic interrupts the 6502 less for memory refresh compared to the old one.

To convert an NTSC machine to PAL, one needs to add a second crystal with a 74LS74 chip and replace the existing one with one slightly faster? or is it slower? In the 1200XL, this will be a chore as there is no provision on the motherboard for the PAL circuitry. Also the modulator will need to be replaced.

 

james

 

The 8bit vs 9bit refresh cycle has nothing to do with the scan rate or system clock. What it does mean is that using "RAS only REFRESH" which is one of two methods supported by most 8-bit DRAMs of the day, the 1200XL ANTIC could only refresh 64k of memory. The later ANTIC used in the 800XL, 65XE, 800XE, XEGS and 130XE machines generated refresh adress "setups" for 256k or (or 9 bits of "ROWS") on the "RAS only refresh" cycle.

 

This is the reason that if you want to upgrade a 1200XL past 64k, you need to either 1) replace the antic with a newer (9-bit refresh) part, or 2)create your own circuit to add the extra bit of "ROW setup" on the refresh cycle. This is the reason that the RAMBO XL has jumper settings for 1200XL...

 

Since the 400, 800 and 1200XL were never sold in Europe, it's probably a safe bet that all PAL ANTIC chips are 9-bit refresh (eg. 800XL, 130XE, etc. which were quite popular in Europe.)

 

The older ANTIC "D" (CO12296 NTSC, CO14887 PAL) generates a 7-bit row address. The newer ANTIC "E" (CO21697 NTSC, CO21698 PAL) generates an 8-bit row address. But it's moot if you use the newer RAS-only on newer 256K/1Mbit DRAMs.

[Beetle]

if you want to upgrade a 1200XL past 64k, you need to either 1) replace the antic with a newer (9-bit refresh) part, or 2)create your own circuit to add the extra bit of "ROW setup" on the refresh cycle.

 

Or you put in a SRAM upgrade. No refresh issues at all

 

Making the 1200XL full PAL needs PAL ANTIC and GTIA, changing the main oscillator AND adding the color clock oszillator for PAL Video, since it can't be taken from system clock like in NTSC systems. PAL XL always have 2 oszillators.

 

Happy modding

Beetle

[MEtalGuy66]

The older ANTIC "D" (CO12296 NTSC, CO14887 PAL) generates a 7-bit row address. The newer ANTIC "E" (CO21697 NTSC, CO21698 PAL) generates an 8-bit row address. But it's moot if you use the newer RAS-only on newer 256K/1Mbit DRAMs.

Heheh. Actually, the extra bit of row adress setup is NEEDED for RAS only refresh. Its not needed for "CAS before RAS" refresh which is the refresh mode (supported by the newer chips, as you said) that tells it to refresh all rows "automatically." This is triggered by CAS being pulled low slightly befre RAS (thus the name) and requires no row adress setup at all.

 

Hmm. this is bringing back some strange memories of MIO troubleshooting....

[sup8pdct]

The difference between the old antic and the new antic as far as I know is the old antic has an 8 bit refresh cycle and the new one has a 9 bit refresh cycle. What it actually means, I am not sure. maybe the new Antic interrupts the 6502 less for memory refresh compared to the old one.

To convert an NTSC machine to PAL, one needs to add a second crystal with a 74LS74 chip and replace the existing one with one slightly faster? or is it slower? In the 1200XL, this will be a chore as there is no provision on the motherboard for the PAL circuitry. Also the modulator will need to be replaced.

 

james

 

The 8bit vs 9bit refresh cycle has nothing to do with the scan rate or system clock. What it does mean is that using "RAS only REFRESH" which is one of two methods supported by most 8-bit DRAMs of the day, the 1200XL ANTIC could only refresh 64k of memory. The later ANTIC used in the 800XL, 65XE, 800XE, XEGS and 130XE machines generated refresh adress "setups" for 256k or (or 9 bits of "ROWS") on the "RAS only refresh" cycle.

 

This is the reason that if you want to upgrade a 1200XL past 64k, you need to either 1) replace the antic with a newer (9-bit refresh) part, or 2)create your own circuit to add the extra bit of "ROW setup" on the refresh cycle. This is the reason that the RAMBO XL has jumper settings for 1200XL...

 

Since the 400, 800 and 1200XL were never sold in Europe, it's probably a safe bet that all PAL ANTIC chips are 9-bit refresh (eg. 800XL, 130XE, etc. which were quite popular in Europe.)

 

The older ANTIC "D" (CO12296 NTSC, CO14887 PAL) generates a 7-bit row address. The newer ANTIC "E" (CO21697 NTSC, CO21698 PAL) generates an 8-bit row address. But it's moot if you use the newer RAS-only on newer 256K/1Mbit DRAMs.

I stand...... errrm..... Sit corrected:)

Hmmmm. wouldn't the 1200xl have the new antic because it's 64K chips has 8 row address lines? The 400/800 use 16K chips which only have 7 address lines but then what about 265k ram upgrades for the 800 and 48K using 64K chips for the 400?

 

James

[MEtalGuy66]

I stand...... errrm..... Sit corrected:)

Hmmmm. wouldn't the 1200xl have the new antic because it's 64K chips has 8 row address lines? The 400/800 use 16K chips which only have 7 address lines but then what about 265k ram upgrades for the 800 and 48K using 64K chips for the 400?

 

James

 

8 bits of multiplexed (row and column) adressing gets you 64k. 9 bits gets you 256k.. 10 bits gets you 1 meg..

 

If ANTIC is unable to generate the required number of bits of ROW adress setups for "RAS only" refresh, then you can either:

 

a)add your own additional binary counter circuitry to create the needed number of bits of ROW adress setups on the refresh cycle.

 

-or-

 

b)do what warerat said: use chips that are new enough to support "CAS before RAS" and just create a "CAS before RAS" situation on the refresh cycle. This type of refresh does not require any adress setups at all. It automatically refreshes all Rows.

Edited September 1, 2007 by MEtalGuy66

[tjlazer]

So on a Rambo XL 256k 1200XL, I would get the 8-bit Antic?

[MEtalGuy66]

So on a Rambo XL 256k 1200XL, I would get the 8-bit Antic?

 

Nope. The RAMBO XL board includes the electrical equivelant of the Claus Bucholz 256k upgrade (The revised version that uses 16k banks.)

 

In addition, there is extra circuitry on the RAMBO XL board that creates a 9-bit row-adress setup on the refresh cycle. This enables the RAMBO XL 256k upgrade to work on the 1200XL with it's original ANTIC chip.

 

SO to answer your question... As far as DRAM refresh goes, you get the equivelant of the 800XL ANTIC.

[sup8pdct]

I stand...... errrm..... Sit corrected:)

 

James

 

8 bits of multiplexed (row and column) adressing gets you 64k. 9 bits gets you 256k.. 10 bits gets you 1 meg..

 

If ANTIC is unable to generate the required number of bits of ROW adress setups for "RAS only" refresh, then you can either:

 

a)add your own additional binary counter circuitry to create the needed number of bits of ROW adress setups on the refresh cycle.

 

 

 

One final question. How does the Ras refresh work? Is Ras held high or low and the 7/8/9 etc bits pulsed or what?

James

[guus.assmann]

I stand...... errrm..... Sit corrected:)

 

James

 

8 bits of multiplexed (row and column) adressing gets you 64k. 9 bits gets you 256k.. 10 bits gets you 1 meg..

 

If ANTIC is unable to generate the required number of bits of ROW adress setups for "RAS only" refresh, then you can either:

 

a)add your own additional binary counter circuitry to create the needed number of bits of ROW adress setups on the refresh cycle.

 

 

 

One final question. How does the Ras refresh work? Is Ras held high or low and the 7/8/9 etc bits pulsed or what?

James

No, just the other way around. (And also for reading/writnig data)

The address is setup and then the Ras is pulsed from high to low = active and then high again.

The low time is specified to a time, hence the maximum usable speed.

Also, all addresses have to be refreshed at a high enough rate.

 

BR/Guus

[MEtalGuy66]

To elaborate on that...

--------------------------------------------------------------------------------------

Lets say we have a DRAM control circuit that employs 10 bits of adressing.

This amounts to 1024k. For our purposes, we will assume that the entire

1024k is accessed as a single contiguous bank of memory.

--------------------------------------------------------------------------------------

 

Imagine the DRAM as a matrix of "cells" defined by

rows and columns. The matrix consists of 1024 (10 bits) of rows,

by 1024 (10 bits) of columns. Each "cell" has the capacity to store one

byte(8 bits) of data. Thus 1024 x 1024 = 1024kilobytes.

 

Signals:

 

RAS- row adress strobe

 

CAS- column adress strobe

 

WE- Write enable

 

Ram Adress bus lines:

A0-A9- 10 bits of adress lines who's states are evaluated as a binary number which defines either a row, or a column within

the DRAM's memory cell matrix.

 

Data bus lines:

D0-D7- 8 bits of data lines. These are either set by the processor/machine to indicate values of data to be written to ram, or

set by the DRAM chip to indicate values of data being READ back from the ram.

 

 

---------------------------------------------------------------------------------------------------------------------------------------------

 

This is how the RAS-only refresh cycle actually works..

 

1.) As Assman said, a row adress is setup on the DRAM adress lines (A0-A9)... This state is usually maintained for at least 100-250ns...

 

2.)About 10-50ns after the row adress setup(approximate- timing may vary from one design to another,) the RAS signal is pulled low. This is signal for the DRAM chips to actually evaluate the Row adress for refresh. The row adress setup must be maintained for a specified amount of time after this point (eg. 100-250ns as stated above.)

 

3.)The specified Row is refreshed by the DRAM.

 

4.)after being held LOW for a certain amount of time,( possibly 100-250ns) RAS is allowed to go HIGH again.

 

--------------------------------------------------------------------------------------------------------------------

 

About the ROW setup on A0-A9

 

This is a binary value (10 bits in this case) indicating a ROW of memory "cells".

 

Refresh cycles happen at regular intervals whenever there are no read or write cycles happening.

 

----------------------------------------------------------------------------------------------------------------------

Explanation of DRAM cycles and differentiation between them

 

RAS, CAS, and WE are instrumental to the DRAM in dermining what type of cycle is being initiated (READ, WRITE, REFRESH).

 

The normal state of these signals is high. They are asserted by being pulled LOW and held for a specified amount of time.

 

memory access cycles

 

If RAS is asserted (and held) slightly before CAS is asserted (and held), this indicates a memory access cycle. At the time that RAS is pulled low, the ROW adress is evaluated based on the state of A0-A9. These states must be held for a certain amount of time after RAS is asserted, but must be switched to states which indicate the COLUMN adress at least 10-20ns before CAS is asserted. The column adress states on A0-A9 must then be held for a specified amount of time after CAS is asserted. During this entire process, it is customary to have the state of WE set either high (read) or Low (write). I believe the actual point when it is evaluated by the DRAM is the same as that of the Column adress. This WE signal determines whether the memory access cycle is a READ or WRITE cycle.

 

On a WRITE cycle, the states of D0-D7 must be set to indicate the binary value of the byte of data which is to be stored in RAM. It is customary to set these states and hold them through the entire write cycle, but I believe the actual point of evaluation is slightly after CAS is asserted. there is a specified time interval which the state of D0-D7 must be maintained after CAS is asserted.

 

On a READ cycle, there is a specified time interval after CAS is asserted that the binary value of the byte of data being read from the byte of memory specified by the previous ROW and COLUMN adress setups will appear on lines D0-D7.

 

refresh cycles

 

if RAS is asserted and CAS is not asserted at all, this commands the DRAM to perform a "RAS-Only Refresh" cycle.

This is described above in the first paragraph. Since this type of refresh cycle only refreshes a single specified ROW in each cycle, there must be logic in place to produce sequential bimary "ROW setups" on each successive refresh cycle, counting from the first row to the last row of the DRAM's "memory cell matrix," then resetting to the first row and repeating the process indefinitely. In terms of the simplest circuit design, this basically amounts to a binary counter circuit triggered once per refresh cycle, and a buffer/line driver (triggered at the correct timing for ROW adress setup)to take the output states of the counter on/off the ram adress bus.

 

If CAS is asserted slightly before RAS, this commands an AUTOMATIC REFRESH or "CAS before RAS refresh".

There is no adress setup needed for this type of refresh. During this type of cycle, ALL ROWS ARE REFRESHED AUTOMATICALLY. This is the "automatic refresh" which is supported by the newer/larger DRAM chips. WHich as you can see, is not really "automatic" in the sense that it must still be initiated by the correct CAS/RAS assertion and timing. It does however negate the need for generation of an incremented ROW adress setup for each cycle.

 

------------------------------------------------------------------------------------------------------------------------------------

 

All of this is much easier to see on a "timeline" type diagram.

 

These timing diagrams are available for any type of DRAM, along with exact specifications for state and timing in the product data sheets.

 

Ok..

 

Now, Warerat will publish an addendum to this which will contain all of the corrections to what I wrote..

 

heheh..

Edited September 4, 2007 by MEtalGuy66