Upgrade a 256K MIO to 1 MB?

[+Larry]

I have the docs for this upgrade which was written by Rich Mier (SPACE), and although the author advises against trying to do it, says that it works. This upgrade uses 1 Mbit DIPS and desolders the original ZIPS from the board. There are also no pics with my docs, so this looks like a pretty "hairy" upgrade. Has anyone here attempted this upgrade?

 

I'm also curious if anyone has upgraded one of these by populating the pcb with additional ZIPs or seen any docs for doing this type of upgrade? Parts cost would be higher and certainly the operational heat load would be higher, but seems like it might be a lot easier. (?)

 

Why would I want to do this? Well, I have two fully-working 256KB MIO's sitting in a box...

 

Thanks,

Larry

[+bob1200xl]

Honestly, with all the problems people have using dynamic RAM on these things, SRAM seems like the memory of choice. From what I recall, the 1 meg MIO is not just a 256K MIO with all the ZIPs populated. It has to be tweaked or something.

 

If you were going to the trouble of mounting DIPs on the thing, just use SRAM - back it up with a battery (or use FRAMs). If you want a 'ton' of memory, use CF cards. Better yet, use them all...

 

Bob

 

 

 

I have the docs for this upgrade which was written by Rich Mier (SPACE), and although the author advises against trying to do it, says that it works. This upgrade uses 1 Mbit DIPS and desolders the original ZIPS from the board. There are also no pics with my docs, so this looks like a pretty "hairy" upgrade. Has anyone here attempted this upgrade?

 

I'm also curious if anyone has upgraded one of these by populating the pcb with additional ZIPs or seen any docs for doing this type of upgrade? Parts cost would be higher and certainly the operational heat load would be higher, but seems like it might be a lot easier. (?)

 

Why would I want to do this? Well, I have two fully-working 256KB MIO's sitting in a box...

 

Thanks,

Larry

[MEtalGuy66]

There is no difference at the PCB level..

 

There is a constant thats changed in the firmware that tells it its got 16 "high byte" banks instead of 4..

 

Any "tweaks" are for stability purposes..

 

If I was to upgrade one from 256 to 1meg, Id probably remove the existing ZIPPs and use 4 256k 30 pin SIMMs.

 

 

Hook the CAS of one SIMM to each of pins 4-7 of U22, and then hook the RAS of one SIMM to each of pins 9-12 of U22..

 

Everything else should be hooked "common" to all 4 SIMMs.

 

I would hook all of the Adress, and Data lines to the solder pads where the original "bank of 8" ZIPPs was..

 

D0-D7 to the data lines (theres 1 per ZIPP), and A0-A7 to the adress (each ZIPP has all of these).

 

A8.. Ok. this is important... A8 (from the SIMMs) should go to pin 4 of U7.. Pins 2 and 3 of U7 should be hooked togther, and pin 1 of U7 should go to pin 8 of U13.. This is a post production mod that was used on ALL MIOs.. It delays the timing of A8 by about 15ns... As long as this little "mod" is already there on your MIO (It should be,) you can just hook A8 to one of the A8 ZIPP solder pads, but Id hook it straight to pin 4 of U7 just to be safe..

 

Also, wherever you decide to get A8 from, add a 33ohm resistor in-line with it...

 

Write Enable from all 4 SIMMs should go to pin 13 of U20..

 

 

Ok.. Thats for those that just wanna "do it" and know that it will work..

 

For those that wanna do it GOOD, wait a few days and Ill draw up an upgrade plan (Or maybe warerat will, if he beats me to it) that will "convert" it to the new MIO's dram control circuit, and you can use a single 1meg SIMM, even one that only uses TWO 1mx4 chips... Talk about a power/heat savings... You will no longer be able to use your MIO to keep your coffee warm, but you wont have to worry about the power input circuits burning up either..

 

If you choose this option, it will be 100% compatable with the expansion board we plan to release.. So if you buy that board, all youd have to do is hook up 2 more wires to the SIMM and use 16megs of RAM..

 

Oh. Last thing Ill say is that with this design, the DRAM is rock solid.. Theres no "flakiness" left... With the old design, it was a real pain to get one stable.. With this new design, I cant get one thats "Unstable".

Edited August 23, 2008 by MEtalGuy66

[+Larry]

Honestly, with all the problems people have using dynamic RAM on these things, SRAM seems like the memory of choice. From what I recall, the 1 meg MIO is not just a 256K MIO with all the ZIPs populated. It has to be tweaked or something.

 

If you were going to the trouble of mounting DIPs on the thing, just use SRAM - back it up with a battery (or use FRAMs). If you want a 'ton' of memory, use CF cards. Better yet, use them all...

 

Bob

 

Hi Bob-

 

Converting this to SRAM or CF sounds neat, but unfortunately over my head. Do you by any chance have an already drawn-up plan to something similar where you've used a CF or SRAM? I could likely follow the logic.

 

-Larry

[+Larry]

There is no difference at the PCB level..

 

There is a constant thats changed in the firmware that tells it its got 16 "high byte" banks instead of 4..

 

Any "tweaks" are for stability purposes..

 

If I was to upgrade one from 256 to 1meg, Id probably remove the existing ZIPPs and use 4 256k 30 pin SIMMs.

 

 

Hook the CAS of one SIMM to each of pins 4-7 of U22, and then hook the RAS of one SIMM to each of pins 9-12 of U22..

 

Everything else should be hooked "common" to all 4 SIMMs.

 

I would hook all of the Adress, and Data lines to the solder pads where the original "bank of 8" ZIPPs was..

 

D0-D7 to the data lines (theres 1 per ZIPP), and A0-A7 to the adress (each ZIPP has all of these).

 

A8.. Ok. this is important... A8 (from the SIMMs) should go to pin 4 of U7.. Pins 2 and 3 of U7 should be hooked togther, and pin 1 of U7 should go to pin 8 of U13.. This is a post production mod that was used on ALL MIOs.. It delays the timing of A8 by about 15ns... As long as this little "mod" is already there on your MIO (It should be,) you can just hook A8 to one of the A8 ZIPP solder pads, but Id hook it straight to pin 4 of U7 just to be safe..

 

Also, wherever you decide to get A8 from, add a 33ohm resistor in-line with it...

 

Write Enable from all 4 SIMMs should go to pin 13 of U20..

 

 

Ok.. Thats for those that just wanna "do it" and know that it will work..

 

For those that wanna do it GOOD, wait a few days and Ill draw up an upgrade plan (Or maybe warerat will, if he beats me to it) that will "convert" it to the new MIO's dram control circuit, and you can use a single 1meg SIMM, even one that only uses TWO 1mx4 chips... Talk about a power/heat savings... You will no longer be able to use your MIO to keep your coffee warm, but you wont have to worry about the power input circuits burning up either..

 

If you choose this option, it will be 100% compatable with the expansion board we plan to release.. So if you buy that board, all youd have to do is hook up 2 more wires to the SIMM and use 16megs of RAM..

 

Oh. Last thing Ill say is that with this design, the DRAM is rock solid.. Theres no "flakiness" left... With the old design, it was a real pain to get one stable.. With this new design, I cant get one thats "Unstable".

 

Hi Ken-

 

I actually had thought of using SIMMs. If you or Warerat could draw up a plan sometime that would be really cool and ever-so-helpful!

 

I suspect there are other folks that could benefit from a plan since there are probably 10 or 20 of the 256 KB MIO's in the field for every 1 MB unit.

 

Thanks,

Larry

[+warerat]

There is no difference at the PCB level..

 

There is a constant thats changed in the firmware that tells it its got 16 "high byte" banks instead of 4..

 

Any "tweaks" are for stability purposes..

 

If I was to upgrade one from 256 to 1meg, Id probably remove the existing ZIPPs and use 4 256k 30 pin SIMMs.

 

 

Hook the CAS of one SIMM to each of pins 4-7 of U22, and then hook the RAS of one SIMM to each of pins 9-12 of U22..

 

Everything else should be hooked "common" to all 4 SIMMs.

 

I would hook all of the Adress, and Data lines to the solder pads where the original "bank of 8" ZIPPs was..

 

D0-D7 to the data lines (theres 1 per ZIPP), and A0-A7 to the adress (each ZIPP has all of these).

 

A8.. Ok. this is important... A8 (from the SIMMs) should go to pin 4 of U7.. Pins 2 and 3 of U7 should be hooked togther, and pin 1 of U7 should go to pin 8 of U13.. This is a post production mod that was used on ALL MIOs.. It delays the timing of A8 by about 15ns... As long as this little "mod" is already there on your MIO (It should be,) you can just hook A8 to one of the A8 ZIPP solder pads, but Id hook it straight to pin 4 of U7 just to be safe..

 

Also, wherever you decide to get A8 from, add a 33ohm resistor in-line with it...

 

Write Enable from all 4 SIMMs should go to pin 13 of U20..

 

 

Ok.. Thats for those that just wanna "do it" and know that it will work..

 

For those that wanna do it GOOD, wait a few days and Ill draw up an upgrade plan (Or maybe warerat will, if he beats me to it) that will "convert" it to the new MIO's dram control circuit, and you can use a single 1meg SIMM, even one that only uses TWO 1mx4 chips... Talk about a power/heat savings... You will no longer be able to use your MIO to keep your coffee warm, but you wont have to worry about the power input circuits burning up either..

 

If you choose this option, it will be 100% compatable with the expansion board we plan to release.. So if you buy that board, all youd have to do is hook up 2 more wires to the SIMM and use 16megs of RAM..

 

Oh. Last thing Ill say is that with this design, the DRAM is rock solid.. Theres no "flakiness" left... With the old design, it was a real pain to get one stable.. With this new design, I cant get one thats "Unstable".

 

Hi Ken-

 

I actually had thought of using SIMMs. If you or Warerat could draw up a plan sometime that would be really cool and ever-so-helpful!

 

I suspect there are other folks that could benefit from a plan since there are probably 10 or 20 of the 256 KB MIO's in the field for every 1 MB unit.

 

Thanks,

Larry

 

Real men use big chips with large non-multiplexed address buses without complicated timing

 

1MB with a pair of 512K SRAM chips is pretty easy. Quick and dirty... Need three ICs, 74LS139, 2x628512 or 2x684000 (or equivalent). Connect both power pins. D0-D7 from CPU bus connected directly to SRAM. A0-A7 from CPU connected directly to SRAM. Both SRAM's should be piggybacked on top of each other (connect all pins), except for pin 20 & 22 on both-- pull these up and make sure they don't touch each other. Pull up pin 1 on MIO U27 and ground it. Pins 2, 5, 6, 9, 12, 15, 16, 19 on MIO U27 to SRAM A8-A15. Pins 2, 7, 16 on MIO U24 to SRAM A16-A18. Connect power pins on 'LS139. LS139 pin 2 to pin 15 MIO U24. LS139 pin 3 to pin 9 MIO U3. LS139 pin 4 to bottom SRAM pin 20 & 22. LS139 pin 5 to top SRAM pin 20 & 22. LS139 ground pins 1 & 15. LS139 pin 14 to pin 3 MIO U4. LS139 pin 13 to pin 6 MIO U4. LS139 pin 10 to SRAM pin 29 (both of them).

 

Which pins on the SRAM are what (address/data/power), the 1 meg MIO ROM, and where/how you mount it is left as an exercise for the reader. There's the logic and you can draw it out if you want. After this you can essentially remove U14, U25, U26, U20, U9, U23, U22, and U21. Hint-- keep U22 and pull up all the pins except power to reuse it so all you need is the SRAM and piggyback that on the ROM (connecting the right pins of course).

 

I haven't built this, but 99.99% sure it is OK and will work. Not responsible if you listen to me and it actually does/doesn't work.

[Mathy]

Hello guys

 

Do you really have to quote everything?

 

Greetings

 

Mathy

[+warerat]

Hello guys

 

Do you really have to quote everything?

 

Greetings

 

Mathy

 

Yes, this is my first time using the internet and I don't know how to do anything.

[sup8pdct]

I have the docs for this upgrade which was written by Rich Mier (SPACE), and although the author advises against trying to do it, says that it works. This upgrade uses 1 Mbit DIPS and desolders the original ZIPS from the board. There are also no pics with my docs, so this looks like a pretty "hairy" upgrade. Has anyone here attempted this upgrade?

 

I'm also curious if anyone has upgraded one of these by populating the pcb with additional ZIPs or seen any docs for doing this type of upgrade? Parts cost would be higher and certainly the operational heat load would be higher, but seems like it might be a lot easier. (?)

 

Why would I want to do this? Well, I have two fully-working 256KB MIO's sitting in a box...

 

Thanks,

Larry

 

I have done this about 17 years ago to a friends unit. I used the Zip chips and an eprom and several small caps.

MANY holes need the solder to be removed. just as many holes need to be re soldered with chips in place.

Getting the $%$$ stable again was the hardest. All I had was a multimeter with a logic function. I found that by placing the probe on places making it slightly more stable, i placed a cap there. Finally got it but it still was a bit temperamental at times.

 

Not the method I would recommend.

 

James

[MEtalGuy66]

Ok.. First of all..

 

1) I am here to tell you... There is no difference between the 256k MIO and the 1meg MIO harware spec, other than the additional ZIPPs and 1 byte difference in the firmware (a constant (labeled ISMEG in the source) that the initialization routines use to dermine whether there are 4 or 16 64k chunks being swapped by the state of the bits 0-3 of $D1E2....

 

2) Any "additional caps" that you see soldered on an MIO are attempts to fine tune the timing of various circuits and work around stability problems.. Many of the problems can often be attributed to the quality of the PHI2 signal comming from the ATARI. The only other variables here are the minimal operational/timing/signal level/signal quality differences between manufacturers of various ICs used on the MIO, the crappiness of the old 1986 era PCB, and the "20 year oldness" of the whole unit.. Also, where the DRAM is directly concerned, adequate DRAM decoupling caps are a CLASSIC design considration, but if you look at the 1meg MIOs that ICD built, there are no additional caps (except the ones provided for on the PCB) for that purpose..

 

3) It makes no sense to use DIP package DRAMS as a replacement for the ZIPPs. Even if you manage to find DIPs that have the exact same timing/stability characteristics as the original ZIPPs, you are talking about a huge amount of soldering to adapt them and MANY potential areas for stability problems.. The MIO's DRAM control circuit is a very temperamental design (to say the least) and operational/timing variations between one manufacturer of obsolete DRAM and another is almost GUARANTEED to effect it..

 

4) We already have the entire circuit worked out to fix all of this:

*It's completeley documented, but I need to draw it up into an "easy to follow" upgrade instructions/diagram (Which I will do in the next day or so).

*Its 100% stable.. I have TRIED to make this thing get errors.. and with various MIOs, and a "mountain" of different SIMMs, I cannot get any instability/errors whatsoever out of it..

*It is 100% compatable to the original 1meg MIO hardware spec.

*You can use ANY 30 pin SIMM (of one meg or larger) that you (or your buddy) may have laying around to upgrade your MIO to 1meg.

*It requires significantly less "wiring" than any other form of memory you'd be able to "wire" in there..

*When the expansion board comes out, original ICD MIOs that have **THIS UPGRADE** willl be able to use the expansion board, and utilize a full 16meg SIMM, just like the "new production" MIO boards that I have been building. Try pricing 16 megs of SRAM..

*This standard is one that we intend to support and stand behind through the expanson board, and the new firmware release. Any other upgrade path you choose is "your baby" support wise..

 

The last thing I would say is that the motivation behind all of the work that we have done over the past 2 years, and continue to do, is to not only EXPAND, but also UNIFY the existing MIO user base under common standards that get us the max functionality without sacrificing compatability, and at a fair price. My hope is that once the remainder of the hardware(the expansion board) and the enhanced firmware is "nailed down," others will join in to support this thing through applications programming, future OS improvements, etc.. If you wish to be part of this "MIO USER BASE," then I would think twice before "bastardizing" anything into a "one of a kind" upgrade..

Edited August 24, 2008 by MEtalGuy66

[+bob1200xl]

The best path is to make a PCB using SOICs (surface mount, little chips) and hardwire it in. Warerat may have the logic correct - we'd just have to try it. Whatever the effort required, a properly working, reliable MIO is much preferrable to a flakey kludge.

 

Maybe what I'm saying is that we're not ready for a 256K to 1 meg upgrade, yet. Don't trash what you have.

 

Bob

 

 

 

Honestly, with all the problems people have using dynamic RAM on these things, SRAM seems like the memory of choice. From what I recall, the 1 meg MIO is not just a 256K MIO with all the ZIPs populated. It has to be tweaked or something.

 

If you were going to the trouble of mounting DIPs on the thing, just use SRAM - back it up with a battery (or use FRAMs). If you want a 'ton' of memory, use CF cards. Better yet, use them all...

 

Bob

 

Hi Bob-

 

Converting this to SRAM or CF sounds neat, but unfortunately over my head. Do you by any chance have an already drawn-up plan to something similar where you've used a CF or SRAM? I could likely follow the logic.

 

-Larry

[+Larry]

The best path is to make a PCB using SOICs (surface mount, little chips) and hardwire it in. Warerat may have the logic correct - we'd just have to try it. Whatever the effort required, a properly working, reliable MIO is much preferrable to a flakey kludge.

 

Maybe what I'm saying is that we're not ready for a 256K to 1 meg upgrade, yet. Don't trash what you have.

 

Bob

 

Hi Bob, Warerat-

 

I certainly appreciate the SRAM info and will file that away with my hardware upgrade docs, but an SRAM conversion is probably better done by someone better versed in electronics than me and thus better prepared to debug, if required. I think Bob is right -- "a 256K MIO in the hand is worth more than a 1 MB in the bush" to paraphrase the old adage.

Thanks,

Larry

[+Larry]

Hi Ken, James-

 

Thanks for the replies. Sounds like the Zip expansion is not a good way to go, either.

 

Ken, sounds like your SIMM expansion is the route to go. I appreciate your time/efforts on this, and eagerly look forward to seeing a plan for the upgrade. It is certainly great to add to the MIO "body of knowledge."

 

-Larry

[MEtalGuy66]

Ok.. You asked for it...

 

Here it is:

 

Warerat and I have spent almost 2 years developing & testing this circuit.

Steve Carden has been running node #3 of his "Inside the 8-bit" BBS on an MIO using this circuit for over a year now with zero problems.

 

If you do this mod, your MIO will be exactly electrically equivelant to the new MIO boards I am currently building and shipping out.. This means that it will be compatable with any future hardware expansions we release.

 

And here is a Service Manual for it:

 

MIO SERVICE MANUAL ver.2.0

 

I was going to wait to release this, but It may be helpful in light of the fact that I'm releasing the upgrade instructions.

 

I am still working on a chapter that involves a comprehensive analysis of PHI2 clock signal quality across a range of ATARI XL/XE models, CPU part numbers, and installed RAM expansions.. But I guess now, Ill just have to release it as an "addendum" when Im done..

 

Anywayze... If anyone finds any problems/mistakes in the upgrade instructions, please let me know immediately so I can correct/resolve the issue.. This circuit DOES work.. It is 100% stable, and most certainly is NOT "flakey" by any stretch of the meaning..

 

Im posting these in the NEW MIO PRODUCTION RUN thread as well..

Edited August 27, 2008 by MEtalGuy66

[+Larry]

WOW!

 

That is an impressive engineering drawing and upgrade instructions. And looking at it, it certainly looks to be well within my skill level.

 

Thanks so much, Ken!

 

-Larry

[+Guitarman]

I guess the next thing would be the binary for the 1meg MIO firmware or a hex edit location of the bit that needs changed?!?!?

[+hunmanik]

I have the docs for this upgrade which was written by Rich Mier (SPACE), and although the author advises against trying to do it, says that it works. This upgrade uses 1 Mbit DIPS and desolders the original ZIPS from the board. There are also no pics with my docs, so this looks like a pretty "hairy" upgrade. Has anyone here attempted this upgrade?

 

With the way this thread has gone maybe you're not interested anymore, but..

 

Do you know the source of the upgrade? Was it from an issue of the SPACE Newsletter? I have most of the SPACE Newsletters (many more than I've put online so far), so I'd be able to scan any pics, if the original doc had pics.

 

I haven't seen Rich for a while, but I'm pretty sure he's still a SPACE member.

[+Larry]

I have the docs for this upgrade which was written by Rich Mier (SPACE), and although the author advises against trying to do it, says that it works. This upgrade uses 1 Mbit DIPS and desolders the original ZIPS from the board. There are also no pics with my docs, so this looks like a pretty "hairy" upgrade. Has anyone here attempted this upgrade?

 

With the way this thread has gone maybe you're not interested anymore, but..

 

Do you know the source of the upgrade? Was it from an issue of the SPACE Newsletter? I have most of the SPACE Newsletters (many more than I've put online so far), so I'd be able to scan any pics, if the original doc had pics.

 

I haven't seen Rich for a while, but I'm pretty sure he's still a SPACE member.

 

Hi Michael-

 

I have seen the upgrade posted in several places, but do not know its exact origin. There were evidently several updates to the upgrade. Mine says "Rev. C." I'll do the SIMM upgrade, but hopefully if you do run across any pics or further updates, you could post them.

 

Thanks,

Larry

[MEtalGuy66]

SPeaking of "Other updates"

 

1) Heres an issue that involves VERY EARLY release ICD MIO boards. I haven't seen many that didn't already have this update, but I have seen a few, so here goes.

 

If you notice on the ICD MIO board (and on the original hand-drawn ICD Schematic,) there is a layout for VR2, which is a small 0.1A 12V regulator. This was to run the phase-locked loop IC (U19) that generates the PHI2 signal when the atari is off. The original U19 IC was the MC14046, which was a 12v part. (I just noticed I got these 2 mixed up in the parts list in the service manual.. I'll correct this).. Anywayze, at some point they decided to switch to the 74HC4046 which is a 5v part. SO what they did was remove the 7812 regulator at VR2, and connect a wire from pin 7 or 8 of J7 to pin 3 (closest to the DRAM area) of VR2.. This energizes the "12v" circuit that powers U19 with 5v.

 

So what you do is: A)replace the 14046 with a 74HC4046. B)remove the VR2 reguilator. C) install a "blue wire" on the back of the board from pin 7 or 8 of J7 to the pin 3 (closest to the DRAM area) solder pad where VR2 used to be.

 

note: you can also remove C42,C43,D1, and D6 (The two 220uF electrolytic caps and two small diodes to the left of VR2 )if you want. This is a voltage-doubler circuit that was used to feed the 12v regulator at VR2.

 

All later MIOs have this "update" and for stability purposes, it really needs be done to any early MIOs that still have the MC14046 and 12v regulator.

 

2) Remove the "tuning cap" at CV1 and replace it with two 68pF ceramic caps in parallel. Also make sure that C17 is a 22pF ceramic cap.

 

3) If there is not already a ceramic cap soldered from pin 6 to pin 8 of U4, install a 68pF cap here too.

 

If your MIO doesnt have these 3 mods, and it's "flakey, but works," Then you really need to do these 3 mods.. It will do alot to "clean up & Standardize" the PHI2 signal and how it is used in the MIO..

 

ALL NEW MIOs THAT CAME FROM ME ALREADY HAVE ALL OF THESE MODS BUILT IN, SO DONT DO IT!

Edited August 27, 2008 by MEtalGuy66

[MEtalGuy66]

Please Re-Download the MIO Service manual. The parts list was totally "out of whack"... I fixed it...

 

same download link as before..

[atariksi]

...

 

Which pins on the SRAM are what (address/data/power), the 1 meg MIO ROM, and where/how you mount it is left as an exercise for the reader. There's the logic and you can draw it out if you want. After this you can essentially remove U14, U25, U26, U20, U9, U23, U22, and U21. Hint-- keep U22 and pull up all the pins except power to reuse it so all you need is the SRAM and piggyback that on the ROM (connecting the right pins of course).

 

I haven't built this, but 99.99% sure it is OK and will work. Not responsible if you listen to me and it actually does/doesn't work.

 

Speaking of ROMs, can't that be a flashable/removeable chip-- just don't like that self-test and would rather not have one or write one that DOES NOT USE RAM while running tests especially the RAM test.

 

Also, is the MIO allowing both ANTIC/CPU accesses simultaneously since PortB bits were limited or is it using some other memory mapped location for banking mechanism?

[+warerat]

Also, is the MIO allowing both ANTIC/CPU accesses simultaneously since PortB bits were limited or is it using some other memory mapped location for banking mechanism?

 

The MIO memory is totally separate (hence, the ability to turn off your machine and the MIO will retain its contents) and has nothing to do with PIA Port B. Its memory is visible 256-bytes at a time at $D600-$D6FF when enabled and has two locations (bank/page) you use to select which section of the 1 MB you see. ANTIC and CPU will always see this memory and there is no way to select one or the other exclusively.

[atariksi]

Also, is the MIO allowing both ANTIC/CPU accesses simultaneously since PortB bits were limited or is it using some other memory mapped location for banking mechanism?

 

The MIO memory is totally separate (hence, the ability to turn off your machine and the MIO will retain its contents) and has nothing to do with PIA Port B. Its memory is visible 256-bytes at a time at $D600-$D6FF when enabled and has two locations (bank/page) you use to select which section of the 1 MB you see. ANTIC and CPU will always see this memory and there is no way to select one or the other exclusively.

 

Isn't 256 bytes limiting for ANTIC use like a text mode or graphics mode?

[MEtalGuy66]

...

 

Which pins on the SRAM are what (address/data/power), the 1 meg MIO ROM, and where/how you mount it is left as an exercise for the reader. There's the logic and you can draw it out if you want. After this you can essentially remove U14, U25, U26, U20, U9, U23, U22, and U21. Hint-- keep U22 and pull up all the pins except power to reuse it so all you need is the SRAM and piggyback that on the ROM (connecting the right pins of course).

 

I haven't built this, but 99.99% sure it is OK and will work. Not responsible if you listen to me and it actually does/doesn't work.

 

Speaking of ROMs, can't that be a flashable/removeable chip-- just don't like that self-test and would rather not have one or write one that DOES NOT USE RAM while running tests especially the RAM test.

 

Also, is the MIO allowing both ANTIC/CPU accesses simultaneously since PortB bits were limited or is it using some other memory mapped location for banking mechanism?

 

Is this a serious question?

 

The MIO doesnt have a built in self test... And has nothing to do with the built in self test in the ATARI XL/XE series.

 

How can you "not use RAM" to run any program, especially a RAM test?

 

How in the hell could the MIO be connected to the PORTB lines of the PIA? The MIo is a PBI device... You think we have some kind of jumper-cable that has to be strung inside your machine and soldered to the PIA chip?

 

NO ATARI can do simultaneous ANTIC/CPU access to ANY RAM because ANTIC halts the CPU when it accesses ram.. DUH!

 

If you are talking about SEPARATE ANTIC/CPU access to extended RAM banks (the 130XE is the only stock machine that can do this, and many ram upgrades disable this feature due to use of bit 5 of PORTB) then once again.... Why would you think a PBI device would influence the operation of the PIA chip?

 

Since your questions dont make any sense, whatsoever... Maybe this will help, even though its not a direct answer..

 

We are considering using flash (instead of EPROM) for the extended firmware that will be present on the planned/upcoming video/ram/clock expansion board. We are not going away from the EPROM on the base MIO for obvious compatability reasons.

 

The memory present on the MIO is nothing resembling a traditional "extended ram upgrade hack"... It uses its own independant registers at $D1E0 and $D1E2 for bank switching, and has nothing to do with PORTB of the PIA...

The MIO extended RAM occupies only 256bytes of the 6502 adress space ($D600-$D6FF) and (on a 1meg model) is switched in 4096 banks of 256bytes each..

[+warerat]

Isn't 256 bytes limiting for ANTIC use like a text mode or graphics mode?

 

Definitely.

 

But I'm not quite following why you'd want to use the MIO memory for ANTIC display stuff as this isn't its intended function. But that being said, there's nothing to keep someone from using the MIO memory that way.