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New GTIA chips!


Curt Vendel

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6 hours ago, TheProgrammerIncarnate said:

Curt just released the schematics here. He also shared the GDS files with me in hope that I could help convert them to verilog. Unfortunately I've been unable to open them as they're an older format of GDSII files.

 

Why he "shared" the GDS files just with you !!!??? Why not make then public? If he does I'm sure somebody, eventually, would be able to process them. And besides, the original GDS files are valuable by themselves to preserve them and make then public.

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33 minutes ago, ijor said:

 

Why he "shared" the GDS files just with you !!!??? Why not make then public? If he does I'm sure somebody, eventually, would be able to process them. And besides, the original GDS files are valuable by themselves to preserve them and make then public.

Maybe @TheProgrammerIncarnate asked him? 

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53 minutes ago, DrVenkman said:

Maybe @TheProgrammerIncarnate asked him? 

 

I guess you don't mean he specifically asked to share the files with him only and not make the public, do you?

 

If you mean that he simply asked for the files, well ... as you can see at this very same thread, many of us have been asking for those chip layout files for years.

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10 minutes ago, ijor said:

I guess you don't mean he specifically asked to share the files with him only and not make the public, do you?

There may be a language barrier here but that’s a pretty convoluted way to misinterpret my comment. :) 

 

I’m suggesting the guy asked Curt directly for a copy of the file, maybe even in person and face-to-face since this person has only a handful of posts and likely knows Curt from someplace other than AtariAge. I am certainly not suggesting he said anything one way or another about making those files public. 

 

Now as for that, why don’t you contact Curt directly and ask him whatever you like? He’s not on AtariAge very much these days but he’s active on the Atari groups on Facebook and his email still works (I got mail from him about a year ago). 

 

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1 hour ago, DrVenkman said:

There may be a language barrier here but that’s a pretty convoluted way to misinterpret my comment. :) 

I’m suggesting the guy asked Curt directly for a copy of the file ...

 

I think I did interpret your comment correctly. I was just being ironic, sorry. Because, again, many of us asked for those files for years, both publicly and privately. So "he just asked him" doesn't sound a reasonable explanation for sharing the files with a single individual and not making them public.

 

Quote

And to add a bit more context - the files linked above are a 15-page high resolution PDF of schematics for “TIA - MARIA - STEPHANIE” from late 1983 through around August 1984. I have no idea how that relates specifically to GTIA.

 

We are not talking about the schematics that he published. We are talking about the chip layout files, including those mentioned in this thread about GTIA and several other chips, still unreleased to the public.

 

Sorry again for being ironic and not too polite. But I really can't understand why all those files aren't released to the public after all those years. Because of the historic and technical value they have, I honestly believe they really belong to the community.

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2 hours ago, DrVenkman said:

I have no idea how that relates specifically to GTIA.

The MARIA-related thread was last bumped in 2010 while this one was more recently active so I posted it here. The GTIA, MARIA, TIA are all in the same vein of Atari custom graphics chips.

2 hours ago, ijor said:

Sorry again for being ironic and not too polite. But I really can't understand why all those files aren't released to the public after all those years. Because of the historic and technical value they have, I honestly believe they really belong to the community.

No biggie. I heard somewhere that Curt was hesitant to release files because he gave them to someone in the past who used them in something closed in proprietary. No idea if that is true or not. Anyway, he shared them with me and Alan S. (not on AA forums) because Alan was wanting to improve the 7800 core for the MiSTer project (an open FPGA emulation system) and because I've been working on automatically turning layout information into schematics/verilog in my own project. I agree 100% that they should be freely available, but I'll wait till Curt decides that they should be. Perhaps a GPL-esque license would ensure they are only used in open projects.

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1 hour ago, TheProgrammerIncarnate said:

I heard somewhere that Curt was hesitant to release files because he gave them to someone in the past who used them in something closed in proprietary. No idea if that is true or not.

 

Not sure that make much sense to me, does it? You want them to be free and public, but because somebody might/will/did use them closed, then you "close" them yourself? For years and years?

 

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Perhaps a GPL-esque license would ensure they are only used in open projects.

 

You can't GPL something that is not yours. And even if you could, copyright has limited to no effect on hardware design. You can't copyright schematics. Well, you can copyright the particular drawing of the schematics in the best case, but not the actual design. Similarly for layout files. You can't even copyright Verilog or HDL files at the extent as if it they would be software.

 

I went already all over this for my own decap and layout reverse engineering stuff. You just have to grow up and understand that releasing something to the public does have a price.  Please note that "you" in this post is not you personally, but in a generic non personal sense.

 

Anyway, most of this stuff at this point has more historic than technical value because most of the information, including layout, was already recovered by reverse engineering. They do belong to a public museum.

 

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On 12/7/2009 at 4:22 AM, Curt Vendel said:

post-23-126015971787_thumb.jpg

 

I've worked in IC design since the early 80's. The Atari chips would have been designed in the mid to late 70's.

 

When an IC design was completed the design was written to a mag tape (as shown above) in  GDS format, which essentially is just a large set of polygons defining each layer of the silicon (diffusion, poly, metal 1, metal 2 etc.). The tapes were physically shipped to companies who created masks (made from glass) used in the wafer fabrication process. One mask per layer.

 

The finalisation of a modern IC design is still called "tape out" today, even though the data is now shipped electronically. The data format is still GDS. I have used GDS viewers at work, however I have never been involved in layout. I got told off by a colleague for calling it "tape ship" but that was probably what it was called in one of my earlier companies.

 

The Atari chips would have been on an old process using NMOS technology. Nowadays we are at 14nm in CMOS. The 14nm (or 28nm or 40nm or 130nm - there are lots of process sizes) defines the minimum feature size which is normally the minimum width of the gate, but there are better definitions online (this is not my area of expertise but wanted to give a rough idea). The Atari chips probably have a feature size of several um, easy enough to see individual transistors under a microscope. Old chips had very few layers. One reason is that the mask cost was very expensive. Nowadays mask costs are still expensive and there are 10 to 15 (my colleagues could give me an accurate number), not only defining the metal connection layers, but the masking layers for intermediate processing steps. This is why ****ing up a chip design - either it doesn't work or has showstopper bugs- has a massive cost, as it not only delays time to market while the bugs are detected and fixed and ICs re-manufactured (and tested), but new masks have to be made (remember these are one of the major costs of manufacture). Nowadays spare flops and gates are littered around a chip. If a bug is found an attempt is made to fix or patch the bug with these spare gates, modifying as few layers as possible. If a fix can be made by only modifying a single metal layer, then only one new mask needs to be made. I might be mis-remembering but a single mask costs around $500k to $1M.

 

Almost all modern fabs will be CMOS (OK there will be specialised fabs supporting analogue or other special processes) and support processes under 100nm. So there is likely slim chance that any fab can even manufacture the old Atari chips, even given that the GDS is available (from Curt). As I mention the major cost would be for the mask set. Now, some old fabs have been donated to universities. I think that this has happened in the UK, and would be surprised if this was not common in the USA. Even so I suspect that they still would be newer than needed by the old Atari chips, however I do not know for sure!

 

I've attached a picture of a mask from an old process (early to mid 90's I guess). It is see-through just like a PCB mask.

 

NOTE: as the process/feature size has shrunk, so the wavelength of light used to be shone through the mask has had to change to shorter and shorter wavelengths. Even so due to "optical" effects, what is nice and square on the mask comes out all rounded on the silicon. Software now tries to compensate for this in advance, so instead of the mask having lots of nice straight line features, the mask has rounded shapes, which after exposure on the silicon wafer end up being much squarer (which is what the designer sees in the layout tool).

 

Use what I have written as a rough guide. I am sure much more accurate information can be found on the web, possibly Wikipedia.

 

regards...

--Atariry

wafer mask.JPG

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On 12/5/2009 at 7:26 PM, Curt Vendel said:

I have finished recovering the GDS stream and reconstructed the GTIA, MARIA, STELLA and several other proprietary Atari chips, now to see if the GDS can be translated to VHDL or if I can find a fab that still does hmos/nmos the original Atari chips can be reproduced at minimum - in SMD sizes...

 

post-23-12600411927_thumb.jpg

 

Curt

Well there is at least one website nowadays (possibly not when you wrote the above) dedicated to the reverse engineering of old chips (google Ken Shirriff).

 

I have seen bits and pieces of the Atari schematics and back then almost all the design was manual, with clever tricks used to get the most out of as few transistors as possible. Some of the digital gates are more analogue than digital. Back then even most of the transistors which made up each digital gate were "sized", that is the designer labelled the length and width of the gate for each transistor. What that means is that there is no easy translation from GDS back to VHDL. Any translation would have to be done manually, one gate at a time, just as explained in Ken Shirriff's blog. Some of the regular structures, such as register sets, might at least be a little easier once the design of one "bit" is understood. Back then the design was also multiple clock phase and the design was highliy dependant upon the capacitance of some internal nodes for it to work correctly. That is why there was normally a FMAX (maximum operating frequency) and FMIN (minimum operating frequency) for NMOS circuits. Certainly many modern CMOS circuits can do down to 0Hz (all clocks stopped) to minimise current, or run at some really low frequency (32kHz), waiting to be woken up.

 

I am not a frequent visitor to this website, but I think I have seen threads where this kind of reverse engineering has taken place of Antic and GTIA in order to get the software emulators to be cycle accurate, and to allow FPGA implementations. So the knowledge to reverse engineer the GDS is certainly around in the Atari community.

 

I for one would like to have a high res wall poster of one of the Atari chips (or even curtains given the aspect ratio!). If you have a high res scan you can get fabric, posters or even canvases printed. This would be a way for Curt to get some money out of his ownership of this data, and recoup some of the costs in extracting and restoring the data. Just a thought.

 

regards...

--Atariry

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I spent 20+ years at IBM writing and maintaining design-rule checkers for VLSI data sets.  "Tape out" was still a commonly used term to denote release to manufacturing, along with "RIT" (release in technology).  Your estimates for mask build are definitely in the ballpark, which is why we'd typically spend weeks analyzing designs for layout rule violations (DRC) and accurate correspondence with the circuit netlist (LVS).  The last few generations of CMOS technology rely heavily on short-wave light diffraction and interference patterns to draw the tiny features during lithography.  This introduced a lot of constraints in not only _what_ you can draw but in its periodicity and orientation. 

 

IBM used their own graphics language "GL1" for many years (complete with EBCDIC text encoding :-)), then switched to GDSII, which was in relatively common use until the early 2000s.   By the time I moved on it had been replaced by OASIS, which is more expressive and has many ways to keep file sizes smaller. 

 

It is indeed unlikely that any fab would be able to simply build a working chip from 40 year old physical data.  Assuming schematics or RTL descriptions are available, you'd be better off synthesizing it for FPGA.  Given access to the appropriate software tools (at $50-100k per seat) and skill set it might be possible to migrate (shrink) the design to a modern technology.  But the total costs would be astronomical, so discussing this is an intellectual exercise at best.

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There is a route - going with MOSIS and submitting your mask in with others and the unused space on the wafer can be used for your chips.   The positive side is you can have a run done in the $25-35K area, the downside - you will only get a school or hobby run of a few hundred chips.    It is an avenue.... still way out of scope for us mere mortals...  But not to worry - I'll win the Powerball lottery someday ;-)

 

 

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So I take it that GTIA and the 6502 are now known in the needed format (GDS?) but not ANTIC, POKEY nor Freddie?  Unsure about PIA.

 

Would be great to have the whole computer done on one die for a couple reasons.  1) Cost savings and 2) a new simple board design similar to a pi zero.  So that includes dual pokeys and maybe both PAL and NTSC GTIA/ANTIC as well. Having native HDMI video from the chip would be a plus. :)

 

 

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On 10/22/2019 at 1:47 PM, Sugarland said:

Would be great to have the whole computer done on one die for a couple reasons.  1) Cost savings and 2) a new simple board design similar to a pi zero.  So that includes dual pokeys and maybe both PAL and NTSC GTIA/ANTIC as well. Having native HDMI video from the chip would be a plus. :)

Granted that would be super cool, but inevitably timing issues would creep in due to the greatly decreased distances between the individual chips. So just like it took creative buffering of certain signals in the original A8's (who's methods varied between the different systems) to make things happy, the same would likely be the case of what you are proposing. However the prototyping required to correct for this would be much more expensive I would imagine. Then there is the cost of the chip manufacturing to think about. And without the benefit of large volume sales, this too would require a high $$$ amount for each custom chip produced.

 

I think the closest we'll get to this is with the FPGA versions we have already seen such as what was done in the Eclaire.

 

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On 10/21/2019 at 1:08 PM, atariry said:

Back then the design was also multiple clock phase and the design was highliy dependant upon the capacitance of some internal nodes for it to work correctly. That is why there was normally a FMAX (maximum operating frequency) and FMIN (minimum operating frequency) for NMOS circuits. Certainly many modern CMOS circuits can do down to 0Hz (all clocks stopped) to minimise current, or run at some really low frequency (32kHz), waiting to be woken up.

 

This is not strictly related to the MOS process or the clocking system used at that time (called two phases non overlapped clock). Flip flops, memory bits, can be static or dynamic, as it happens with SRAM or DRAM chips respectively. Static memory holds the content with a voltage loop, dynamic memory just by capacitance and must be refreshed frequently enough. The same type of memory bits are used inside chips. If a chip uses only static flip flops, then it is fully static and it has no minimum clock frequency. That could have been implemented at the time with NMOS chips, but there was no interest in that feature, and would have been too expensive because static ram takes more transistors than dynamic ram.

 

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... but I think I have seen threads where this kind of reverse engineering has taken place of Antic and GTIA in order to get the software emulators to be cycle accurate, and to allow FPGA implementations. So the knowledge to reverse engineer the GDS is certainly around in the Atari community.

 

I reverse engineered the layout of the whole Atari 8 bit chipset.

 

This is the main thread for ANTIC, with high rez die image, reverse engineered schematics and layout:

 

The digitized layout was meant for reverse engineering the logic. Some work would be required to use for fabbing NMOS chips. At the time I didn't think somebody would be interested. And probably is better to use an FPGA/CPLD replacement instead of a full custom chip. Nowadays is no big deal to put a CPLD (non volatile FPGA) with voltage level shifters in a small board that would fit a DIP 40.

 

 

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