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matthew180

Assembly on the 99/4A

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1 hour ago, PeteE said:

Thanks, Tursi.  I've grown to trust Classic99 based on how much work you've done to make it cycle accurate.

Well, to make the cycle counts accurate, anyway. It doesn't emulate every internal cycle like MAME does... though it's getting closer all the damn time. ;)

 

I think it's fixed, so I'll push the new version shortly.

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In reviewing how CLR @VDPSTA works on the 9900 versus 9995 and what @PeteE is trying to do, I thought about using ABS @VDPSTA instead which requires reading VDPSTA with both CPU’s.

 

In reviewing ABS, I note that it is the original value (source operand) that sets the status register bits 0-4 and not the result.  Is this how MAME, @mizapf, and Classic99, @Tursi, work?

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hehe, it wouldn't work terribly well if it didn't. :) That's as documented.

 

 

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@Tursi, I think ABS is rarely used.  Do we have a chart of instruction frequency?  ABS is special.  Is there any other assembly instruction that sets status bits on source operand?

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55 minutes ago, Jeff White said:

@Tursi, I think ABS is rarely used.  Do we have a chart of instruction frequency?  ABS is special.  Is there any other assembly instruction that sets status bits on source operand?

 

All of the immediate instructions except LIMI and LWPI do: AI ANDI ORI LI CI(not sure how you would characterize this one?)

 

...lee

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Got a question.

 

Does the LOAD opcode >05 return anything to the PAB in VRAM beyond the status byte for a Program Image file?  Would the Myarc HFDC return anything more?  Perhaps the program start address and length of file?  This may be something very specific to the Myarc HFDC.

 

I've not been able to find any specific notes on the LOAD opcode, and an example of a file I am using suggests there is more going on.

 

Beery

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35 minutes ago, Jeff White said:

In reviewing how CLR @VDPSTA works on the 9900 versus 9995 and what @PeteE is trying to do, I thought about using ABS @VDPSTA instead which requires reading VDPSTA with both CPU’s.

I looked at ABS also, but initially dismissed it because the number of clock cycles isn't constant based on the source argument: (MSB=0) 12 cycles, (MSB=1) 14 cycles.  The MSB in the VDPSTA register (interrupt flag) will be 0 during scanout, so it would actually be fine.  Thanks!

 

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6 hours ago, Jeff White said:

@Tursi, I think ABS is rarely used.  Do we have a chart of instruction frequency?  ABS is special.  Is there any other assembly instruction that sets status bits on source operand?

My point is it's documented to operate that way even in the Editor/Assembler manual, which is light on detail. ;)

 

We did have someone run a summary of instruction frequency a few years ago, at least I think it was here on AA...

 

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12 hours ago, BeeryMiller said:

Does the LOAD opcode >05 return anything to the PAB in VRAM beyond the status byte for a Program Image file?  Would the Myarc HFDC return anything more?  Perhaps the program start address and length of file?  This may be something very specific to the Myarc HFDC.

Just recently (it was in the context of copying Adventure files from cassette to disk) I learned that LOAD does not deliver the number of actually loaded bytes, which really surprised me. This would have been trivial to achieve in the DSR; the GeneveOS XOP, however, does return the image size.

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