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ijor

Flags on decimal mode on the NMOS 6502

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This is an article I wanted to publish some time ago, about a quirk of the 6502 CPU. I was waiting for finding the time to make a few enhancements to the article, but I never found the time. So I am publishing as it is as this time, it shouldn't be that bad.

 

The article is about the odd behavior of the CPU flags after performing an addition on decimal mode. This is a known quirk/bug of the NMOS parts, including Sally. This article explain what wasn't (AFAIK) known, the reason behind this odd behavior, or in other words what the hardware really does and why.

DecimalMode-6502.pdf

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I received a couple of comments suggesting that I didn't make myself clear about the actual content and purpose of the article.

 

The article is not exactly about the behavior of the flags. Since long ago that it is known exactly how to compute the flags (mostly done for emulation purposes). The article is about the reason of the odd behavior, and about what the hardware exactly does to reach this behavior.

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I received a couple of comments suggesting that I didn't make myself clear about the actual content and purpose of the article.

 

The article is not exactly about the behavior of the flags. Since long ago that it is known exactly how to compute the flags (mostly done for emulation purposes). The article is about the reason of the odd behavior, and about what the hardware exactly does to reach this behavior.

 

Can you tell EXACTLY how you compute the V flag. Machine Language for Beginners book page 68 states only 5 instructions affect it and they relate to twos-complement. I guess ADC and SBC are two instructions. What are the other 3? CLV/BIT don't seem to relate to twos complement. What does shift instructions do to V flag?

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I don't know what twos-complement means or what they meant by it but these 5 instructions IMHO are ADC,SBC,CLV,BIT as you said and the last one PLP.

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I don't know what twos-complement means or what they meant by it but these 5 instructions IMHO are ADC,SBC,CLV,BIT as you said and the last one PLP.

 

Plus, the original 6502 has a "Set Overflow" Pin. Through it, external hardware can set the flag. Useful for extremely fast polling loops like

 

LOOP: BVC LOOP

 

This loop takes only 3 cycles. For example, the Commodore disk drives use it to find out when a byte has been read completely from the disk, since a normal

 

LOOP: BIT $XXXX
     BNE LOOP

 

takes 7 cycles, which would be too slow, so the byte could be lost since one bit of the next byte has already come in by the time you get to read the byte from the hardware register.

 

I'm not sure it the S.O. pin is connected to anything in the Ataris, but most computers leave it unconnected.

Edited by tearex

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That website is claiming that it takes 3 cycles to do a hardware SO pin check:

 

LOOP: BVC LOOP

 

and 7 cycles to do it in software:

 

LOOP: BIT $XXXX

BNE LOOP

 

Suppose the bit you are examining in the latter changes after the BIT instruction, then that would mean 3 cycles + 4 cycles + 2 cycles (no branch) = 9 cycles. And suppose it changes on first three cycles of BIT instruction, then flags would be correct and it would take 3 more cycles to exit out of the loop. So someone goofed up. A subcycle analysis of the first one is also needed if SO changes during BVC execution.

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Doesn't really matter, it's quicker than the traditional way regardless.

 

I'd reckon the test occurs on 2nd cycle... 6502 only really does opcode fetch on first.

 

If so, then the worst case is if SO hits on 3rd cycle, which would mean that cycle gone, followed by 2 more cycles for the next BVC which will fail/fall through for 2 cycles used = total of 3 cycles.

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