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What is the real core of ATARI's 6502C CPU

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While updating an 1980s sourcebook in German language with a team within ABBUC we tried to clear some fog around the CPUs of the 400/800/XL/XE/XEGS machines - not really successful so far. Some of our team working on that issue tried to find hard facts or sources to prove what's really inside. Let's see what we'd found:

 

- 400/800 NTSC machines all seem to be equipped with 6502B CPUs, meaning 3MHz versions according to the manufacturer's coding. Why is that where 6502A (2MHz) would have been sufficient to do the job?

 

- 400/800 PAL machines so far seen from the inside do have 6502C Sally CPUs.

 

- for 400/800 SECAM we need to know ...

 

- all the rest is equipped with 6502C Sally CPUs, but what is the real core of the Sally CPU?

 

'C' points to a 4MHz version, which had been offered by some manufacturers back then - but is kind of overdesigned by far. A 'B' version also seems to be too much since running a CPU at 1.77 or 1.79 MHz is well done with a 'A' version, designed to run at 2MHz.

 

So

 

1. So what is hidden in Sally - type A, B or C? (ehm, just to make it clear, it's not about the HALT signal here ...)

 

2. Do 400/800 NTSC machines run properly using 6502A CPUs?

 

Additionally, since ATARI 'til the Tramiel era always was driven by "Power without the price" it seems unikely they used CPUs at remarkably higher costs for a "low power issue", where lower cost CPUs would have done the job.

 

If anybody can provide hard facts and/or documents to clear up the fog, please be so kind to send me a note by pm or e-mail me via ABBUC.

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1. So what is hidden in Sally - type A, B or C?

 

I'm not sure the question is correctly formulated.

 

Designations like 6502, 6502A, 6502B are speed grades. And speed grades usually are not different cores, it is just a matter of testing. When MOS (or an authorized source) manufactured the 6502, it always targeted the best possible grade, it didn't run separate processes. After fabrication, the devices are tested. Some comply with the specifications for "B" speed grades, and are then marked and sold as such. Others fail a "B" qualification, but they are good enough for "A", etc, etc.

 

So you can't say exactly which speed grade (let alone, which core) Sally is. The only thing that makes sense to ask, is which kind of testing they applied (and I'm afraid I don't know).

 

Btw, regarding testing, I seem to recall reading (here?) about a big batch of Sally chips that failed when they become hot?

 

- 400/800 NTSC machines all seem to be equipped with 6502B CPUs, meaning 3MHz versions according to the manufacturer's coding. Why is that where 6502A (2MHz) would have been sufficient to do the job?

 

I believe this question was raised a couple of times, here and/or in the newsgroup. I don't recall reading any authoritative answer. One idea that makes sense, is that the difference between the 6502B speed grade and the 6502A one, is much more than the max frequency. Most of the specifications, not just the frequency, are better. This means such things as faster setup and hold timings. So it is possible that Atari engineers decided that they need the specifications (the other ones, not the max frequency) of the 6502B part.

 

in my book A stands for 1MHz, B for 2

C in 6502C stands for CUSTOM

 

In which book have you seen that? In all the datasheets I've seen "A" is 2 MHz and "B" is 3 MHz. Then some include the "C" speed grade for 4 MHz, others do not.

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My understanding also was A/B means 1/2 MHz certified.

 

I can't recall any computer, console, arcade or otherwise that ran a DIP40 6502 above 2 MHz.

 

Does 400/800 really have Sally in PAL machines? The whole point of Sally was to reduce the chip count by integrating the logic of those several 74LS ICs to hold the clock low, that should then mean both machines would be vastly different.

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There are two 6502 processors with a "C" in the name.

6502C and 65C02.

The 6502C was a standard (pre 65C02) 6502 with a custom pinout for Atari that added a Halt pin.

The 65C02 is a conventional 6502 pinout but with the slightly improved/fixed instruction set.

<edit>

Actually, I believe there are several versions of the 65C02 but some are micro-controllers.

The "C" does not refer to a speed rating but to die process... CMOS.

<edit>

Given the clock speed of the Atari, I would guess the 6502C is based on the 6502B but with added logic to disable the clock signal.

Edited by JamesD

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I believe this question was raised a couple of times, here and/or in the newsgroup. I don't recall reading any authoritative answer. One idea that makes sense, is that the difference between the 6502B speed grade and the 6502A one, is much more than the max frequency. Most of the specifications, not just the frequency, are better. This means such things as faster setup and hold timings. So it is possible that Atari engineers decided that they need the specifications (the other ones, not the max frequency) of the 6502B part.

I've seen mixed information on this, but some points to the "6502" (no letter) being 1 MHz, the "A" model being 2 MHz, "B" being 3 MHz, "C" 4 MHz... though I'm not sure whether that's from confused documentation applied from the 65C02. (ie 65C02A would be 2 MHz, B 3 MHz, C 4 MHz, etc)

http://web.archive.org/web/20080614235008/http://www.cpu-museum.com/650x_e.htm

 

That is how the Z80 was labeled though: "Z80" (no letter) for 2.5 MHz, "A" for 4 MHz, "B" for 6 MHz, "C" for 8 MHz.

 

 

in my book A stands for 1MHz, B for 2

C in 6502C stands for CUSTOM

 

In which book have you seen that? In all the datasheets I've seen "A" is 2 MHz and "B" is 3 MHz. Then some include the "C" speed grade for 4 MHz, others do not.

The 6502C "Sally" that Atari used was not a MOS product, but a custom/licensed in-house Atari derivative, so if there was a "6502C" as such, it was not thesame one that Atari ever used.

Edited by kool kitty89

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6502C being Atari only sounds plausible.

 

I don't know if any other 6502 derivative used the same philosophy to halt the processor. C64 uses a mix of interleaved access and holding /RDY when longer bursts of DMA are needed.

The Plus/4 receives it's clock from TED, and there's no /HALT available there either - DMA on that machine is done by TED feeding the CPU longer phase pulses which effectively halves it's speed... IIRC badlines are handled by using /RDY also.

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6502C being Atari only sounds plausible.

 

I don't know if any other 6502 derivative used the same philosophy to halt the processor. C64 uses a mix of interleaved access and holding /RDY when longer bursts of DMA are needed.

The Plus/4 receives it's clock from TED, and there's no /HALT available there either - DMA on that machine is done by TED feeding the CPU longer phase pulses which effectively halves it's speed... IIRC badlines are handled by using /RDY also.

Any idea what they used on the 65C02, 65816, or some custom derivatives like the PCE's Hudson Soft HuC6280, SNES's Ricoh 5A22, or NES's Ricoh 2A03?

 

It looks like the standard 65816 and 65C02 both lack formal halt lines, not sure about the custom implementations though.

Edit: same for NEC/Hudson's implementation, but I don't see anything definitive for Nintendo/Ricoh's stuff.

Edited by kool kitty89

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Should be in the Datasheets.

 

It's weird... the Atari implementation via Sally seems to be the best compromise - no external assistance is needed, the only cost is a bit of internal circuitry that probably equates to less than your typical 74LS device.

 

The /RDY strategy has the weakness that you usually lose those extra couple of cycles if doing a DMA burst because it has to be asserted early to guarantee that RMW instructions have finished and freed up the bus.

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Appendix I of the book "Understanding the Apple II" mentions that Wozniak had originally tried a DMA setup like the Atari, where the display circuitry would preempt the 6502 for 40 cycles for each scanline. Apparently he had to abandon it because he kept running into issues with the dynamic circuitry in the 6502 failing if the CPU was stopped too long, and even if it did work, it could stop working as the CPU aged. I wonder if it's possible that Atari hit this problem and used higher rated parts to avoid it. A wide mode 2-5 line could definitely halt the CPU that long.

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Strange.

 

In theory you could halt the CPU with a combination of WSYNC and DMA for almost an entire scanline.

Plus using VSCROL tricks you can create 240 badlines in succession - I tried that as a test to try and make the DRAM Refresh fail (didn't work).

 

Maybe the 6502A design had a flaw that was fixed in the B version.

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On the NMOS versions the 6502 registers are dynamic, if the CPU is halted to long it forgets the register contents, that's were the dummy memory fetches are used, to refresh the internal registers..

 

I think that applies only to the NMOS ones actually, since they by definition would be dynamic rather than static, hence the limits on minimum clocks speeds and the amount of time Phi2 could be held low..

 

I guess the 65C02 won't have that problem since it'll be a static chip, but earlier NMOS(dynamic) would..

 

 

 

 

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I just looked in my Rockwell Controller Products Data Book, dated July 1987.

 

CMOS - digit after R65C02XYZ

X - Package type, C-40pin Ceramic DIP, P-40pin Plastic DIP, J-44pin PLCC

Y - Speed, 1 = 1Mhz, 2 = 2Mhz, 3 = 3Mhz, 4 = 4Mhz (nothing higher mentioned)

Z - Temp Range, Blank = 0C - +70C, E = -40C - +85C, M = -55C - 125C

 

NMOS - digit after R6502XYZ

X - Speed, No Letter = 1Mhz, B = 2Mhz, C = 3Mhz (nothing higher mentioned)

Y - Package type, C-40pin Ceramic DIP, P-40pin Plastic DIP

Z - Temp Range, Blank = 0C - +70C, E = -40C - +85C

 

Unfortunately I no longer have my MOS books...

 

sloopy.

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The 65816 has a Buss Enable line that allows you to drop the CPU off the buss. You can also stop the clock for as long as you like.

 

Bob

 

 

 

6502C being Atari only sounds plausible.

 

I don't know if any other 6502 derivative used the same philosophy to halt the processor. C64 uses a mix of interleaved access and holding /RDY when longer bursts of DMA are needed.

The Plus/4 receives it's clock from TED, and there's no /HALT available there either - DMA on that machine is done by TED feeding the CPU longer phase pulses which effectively halves it's speed... IIRC badlines are handled by using /RDY also.

Any idea what they used on the 65C02, 65816, or some custom derivatives like the PCE's Hudson Soft HuC6280, SNES's Ricoh 5A22, or NES's Ricoh 2A03?

 

It looks like the standard 65816 and 65C02 both lack formal halt lines, not sure about the custom implementations though.

Edit: same for NEC/Hudson's implementation, but I don't see anything definitive for Nintendo/Ricoh's stuff.

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I repeat. According to all official datasheets I've seen, 6502B is a 3 MHz part, and 6502C is a 4 MHz part. Again, that's what the official documenatation from the actual chip designer and manufacturers claim. Attached are 3 extracts from 3 different datasheets. One from Commodore Semiconductor Group (MOS itself), Rockwell and Synertek:

 

post-6585-129372496474_thumb.jpg post-6585-129372497302_thumb.jpg post-6585-129372498078_thumb.jpg

 

So 6502C is the fastest 6502 speed grade. And even when a bit rare, I believe there are a few pictures online. Atari used, internally the same name/number for Sally. But that's an internal Atari nomenclature.

 

Please don't bring the CMOS parts, they were developed later and by other companies.

 

Given the clock speed of the Atari, I would guess the 6502C is based on the 6502B but with added logic to disable the clock signal.

 

Sorry, but for reasons I explained above, this sentence is non-sensical. You can't make a derived part from a specific speed grade.

 

In theory you could halt the CPU with a combination of WSYNC and DMA for almost an entire scanline.

Plus using VSCROL tricks you can create 240 badlines in succession - I tried that as a test to try and make the DRAM Refresh fail (didn't work).

 

WSYNC doesn't stop the clock (as DMA with HALT does). So it is not relevant for this purpose.

 

Using a faster speed grade for allowing a longer period with the clock stopped doesn't make much sense. In the worst case, it should be the other way around.

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ijor,

thats what it looks like in my book, and yes i am using the dead tree edition, not a scan i got off the inet...

 

sloopy.

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I just looked in my Rockwell Controller Products Data Book, dated July 1987.

...

NMOS - digit after R6502XYZ

X - Speed, No Letter = 1Mhz, B = 2Mhz, C = 3Mhz (nothing higher mentioned)

Y - Package type, C-40pin Ceramic DIP, P-40pin Plastic DIP

Z - Temp Range, Blank = 0C - +70C, E = -40C - +85C

 

So you are saying it doesn't mention the "A" speed grade?

 

Strange, and it sounds like a mistake in the manual. At the very least, it is known that the Rockwell R6502A exists (several pictures available online).

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I just looked in my Rockwell Controller Products Data Book, dated July 1987.

...

NMOS - digit after R6502XYZ

X - Speed, No Letter = 1Mhz, B = 2Mhz, C = 3Mhz (nothing higher mentioned)

Y - Package type, C-40pin Ceramic DIP, P-40pin Plastic DIP

Z - Temp Range, Blank = 0C - +70C, E = -40C - +85C

 

So you are saying it doesn't mention the "A" speed grade?

 

Strange, and it sounds like a mistake in the manual. At the very least, it is known that the Rockwell R6502A exists (several pictures available online).

 

yeah typo no letter= 1 Mhz, A = 2Mhz, B=3Mhz... my bad...

 

sloopy.

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Given the clock speed of the Atari, I would guess the 6502C is based on the 6502B but with added logic to disable the clock signal.

 

Sorry, but for reasons I explained above, this sentence is non-sensical.

It's nonsensical, no hyphen.

 

You can't make a derived part from a specific speed grade.

I'm going to disagree and a clarification of my original statement is definitely in order since "based" is pretty open to interpretation.

 

I do agree that the different speed grades are based on one chip layout.

Layouts were hand taped at that time. I'm sure the layout itself was the same between speed versions prior to the synthesized versions that came out in the 80's, and any derived part like the Atari 6502C was probably a copy of the old layout with the HALT modification added by re-taping that part of the chip.

 

However, you have stated that the difference in speed is determined by testing the parts. I remember Ohio Scientific (or a reseller) advertising a high speed ION implanted 6502 option. That implies some sort of difference in manufacturing existed between speed grades rather than just testing the parts. A quick search on ION implanted semiconductors does return a lot of results so I don't think it was just made up.

I would also think that relying on testing alone would result in a lot of unusable parts for Atari which would be very costly. Some sort of difference in manufacturing to guarantee parts work at the required speed would be likely.

 

If differences in manufacturing did exist for different speed grades of 6502s it is not nonsensical, a derived part needing to run at 2MHz would use the same manufacturing process as the 2MHz part... which I identified as B when it should have been A. But then you said "You can't make a derived part from a specific speed grade" which would be false since you can base it on a different manufacturing process used by a specific speed grade.

 

Now, I'm not saying that speed testing did not take place or that there is any difference in the manufacturing process between the 6502 and 6502A. I'm just saying that the Atari 6502C would have been based on the same same manufacturing process as the 2MHz 6502. And technically, it would also be based on the same layout but with the HALT changes. I just stated it poorly.

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On the NMOS versions the 6502 registers are dynamic, if the CPU is halted to long it forgets the register contents, that's were the dummy memory fetches are used, to refresh the internal registers..

 

I think that applies only to the NMOS ones actually, since they by definition would be dynamic rather than static, hence the limits on minimum clocks speeds and the amount of time Phi2 could be held low..

 

I guess the 65C02 won't have that problem since it'll be a static chip, but earlier NMOS(dynamic) would..

The 6809 had the same issue. I think it could hold contents for at least 13 clock cycles or something like that.

 

The HALT pin on the Atari 6502C would have to keep refreshing the registers while pausing the buss accesses. I'd like to see how some of the 6502 cores that support the Atari chip pinout handle this. It would be interesting to see how complicated it is.

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I do agree that the different speed grades are based on one chip layout. Layouts were hand taped at that time. I'm sure the layout itself was the same between speed versions prior to the synthesized versions that came out in the 80's, and any derived part like the Atari 6502C was probably a copy of the old layout with the HALT modification added by re-taping that part of the chip.

 

It is not just that the different speed grades use the same layout, but they use the same masks, and they are mixed sometimes in the very same waffer. This is true even today, not just in the old days when layout was done by hand. Speed grades are a simple consequence of the imperfections of chip manufacturing. It is natural that some days, some waffers, some particular dies would be better than others. And unless you want to market them at the minimum common denomimator, you inevitably get speed grades.

 

Of course that there are exceptions. A few devices were manufactured with extra features in the fastest speed grades (or at least, those features were enabled and supported). We also have modern Intel/AMD CPUs that have speed locking. But these are exceptions. There are also some cases when the fastest speed grades are produced as a shrink process. But again, it is the exceptional case. For almost every case, speed grades are just a matter of testing, they are manufactured all together.

 

A quick search on ION implanted semiconductors does return a lot of results so I don't think it was just made up.

 

Every single 6502 has Ion implantation.

 

I would also think that relying on testing alone would result in a lot of unusable parts for Atari which would be very costly. Some sort of difference in manufacturing to guarantee parts work at the required speed would be likely.

 

The ratio of fast to slow parts is not constant. When a specific silicon process is implemented, most dies came out so bad that can't be even used. When the process matures, the yield is higher, and at some point most dies comply with the fastest speed grade(s). Atari manufucatured Sally several years later, it is very likely that the fab process was mature enough by then.

 

If differences in manufacturing did exist for different speed grades of 6502s it is not nonsensical...

 

Yes, it is not completely impossible, I agree. But it is very unlikely that there were any manufacturing differences.

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On the NMOS versions the 6502 registers are dynamic, if the CPU is halted to long it forgets the register contents, that's were the dummy memory fetches are used, to refresh the internal registers..

 

The HALT pin on the Atari 6502C would have to keep refreshing the registers while pausing the buss accesses.

 

Actually the main NMOS 6502 registers (such as X,Y,A,SP) are static, not dynamic. There are other internal dynamic cells that would break if the clock stopped for too long. The dummy fetching has nothing to do with any static or dynamic feature, it is because the design is such that the 6502 it is always performing a memory access cycle.

 

When HALT is active, the CPU won't do anything because its clock would be stopped. This is done externally on the 400/800, or internally when using Sally.

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Actually the main NMOS 6502 registers (such as X,Y,A,SP) are static, not dynamic.

 

Correcting myself. They are actually semi static (or semi dynamic), which in this context means they depend on a single phase of the clock. I thought that the phase is the one that is always ON when halted, but seems I was wrong and it is the other way around. Meaning that the registers would forget their content if HALT is active for too long.

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