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What is the real core of ATARI's 6502C CPU

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one thing to consider when thinking about atari 6502C

clock is not gone while halt is asserted, so you can't really tell without going all that trouble ijor made for Antic (decaping and microphotography for a start, ending up with schematics) if circuit is in static mode, or if its repeating last cycle internally

 

considering the fact that this is nmos logic part and limitations of this technology (need a clock >100khz or so, or it forgets what it suppose to do) i would say it repeats last cycle it executed with some internal logic disabled by one mean or the other

 

some prove of that may lie in tests that were made for antic and hscroll bug, when halt was asserted constantly for most of scanline

if clock internally would be stopped for that long, cpu should have gone into the bushes, but it didn't, istead it executed its code as it should

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Could it be that the 2 MHz failed Sally was repackaged as a 6507 for 2600s and disk drives?

 

Leave /HALT alone and it behaves just like a normal 6502, doesn't it?

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it does, and surely a way of reducing production costs

there were other versions of 6502 in dip28 too with missing bits here and there

i don't think that reducing PC size for few bits would gain them a lot in die size terms, so if it wasn't worth the effort, then production dropouts utilisation might be a key factor here

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Should be in the Datasheets.

 

It's weird... the Atari implementation via Sally seems to be the best compromise - no external assistance is needed, the only cost is a bit of internal circuitry that probably equates to less than your typical 74LS device.

 

The /RDY strategy has the weakness that you usually lose those extra couple of cycles if doing a DMA burst because it has to be asserted early to guarantee that RMW instructions have finished and freed up the bus.

 

Maybe it got to the point that the 65C02 was preferable so it was unnecessary to even bother the revised versions featuring internal refresh/halt circuitry. (being fully static could allow READY to be used freely as halt)

 

The 65816 has a Buss Enable line that allows you to drop the CPU off the buss. You can also stop the clock for as long as you like.

Right, the CMOS versions could use READY as HALT would be without any refresh issues. (neat addition to the 816 though)

 

 

 

Given the clock speed of the Atari, I would guess the 6502C is based on the 6502B but with added logic to disable the clock signal.

 

Sorry, but for reasons I explained above, this sentence is non-sensical. You can't make a derived part from a specific speed grade.

No, it makes perfect sense (ie same 6502 core as sued when the "B" speed grade was introduced -as Atari was using that version)... though if the B (and later A/etc) was identical to early model dies, the comparison would be moot anyway. (any such changes would be parallel to the speed increase -the speed increase would be predominantly limited by manufacturing process limitations and yields)

 

But the point is that the Atari "6502C" (C for custom and denoting the Atari created SALLY chip) would not be the same as the standard MOS (etc) 6502C speed grade and the "C" would not have anything to do with speed grading whatsoever.

As such, it would mean (as seems to be the case), that there are 2 unrelated "6502C" designations referring to different things. (1 a normal 6502 speed grade and the other an Atar-specific design, perhaps labeled as such before MOS/3rd parties were even producing "C" speed graded CPUs -which would explain the confusion-)

 

Atari's "6502C" was not a standard MOS/3rd party part, but a custom Atari design. (presumably they licensed the 6502 core to do such -they did other custom 6502 stuff like the ASIC based version in the "JAN" single chip 2600)

 

Using a faster speed grade for allowing a longer period with the clock stopped doesn't make much sense. In the worst case, it should be the other way around.

It would if there were changes made to the die along with the higher speed grade (changes that may also have been present on lower rated models later on), but that's just idle speculation. (it could have simply been the availability of "B" model CPUs of the time, or some other reason)

 

 

 

 

It is not just that the different speed grades use the same layout, but they use the same masks, and they are mixed sometimes in the very same waffer. This is true even today, not just in the old days when layout was done by hand. Speed grades are a simple consequence of the imperfections of chip manufacturing. It is natural that some days, some waffers, some particular dies would be better than others. And unless you want to market them at the minimum common denomimator, you inevitably get speed grades.

Yes, assuming early models didn't use different dies for other reasons. (may have been an early modifcation that only changed the masks used for certain grades -or initially as such before being applied across the board).

 

Regardless of that, the 6502C (SALLY) used by Atari WAS indeed using a different mask than normal MOD/3rd party 6502s, and not the same as commercial "6502Cs" as such.

 

 

Could it be that the 2 MHz failed Sally was repackaged as a 6507 for 2600s and disk drives?

 

Leave /HALT alone and it behaves just like a normal 6502, doesn't it?

The same could have been true for dies that didn't pass the speed spec requirements needed for SALLY. (but would be fine for the lower speeds used in the disk drives and VCS -though the VCS's clock rate was above the official tolerances for a true 1 MHz part, so they'd need to be graded for at least ~1.2 MHz as such)

Edited by kool kitty89

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A quick search on ION implanted semiconductors does return a lot of results so I don't think it was just made up.

 

Every single 6502 has Ion implantation.

So that advertisement was just marketing to ask more money for a CPU.

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Thank you to everybody for this vivid discussion here. So far it didn't lead to a qualified source, which somehow reminds me of some similar discussions during the last 25 years.

 

Topic 1 may be never unrevealed until some docs in the atari museum might be found ...

Or may be the guys who did the "slicing" of the chips (sorry, cannot remember the project page) will discover what is really inside Sally.

 

How about topic 2? Did anybody give it a try?

 

So

 

1. So what is hidden in Sally - type A, B or C? (ehm, just to make it clear, it's not about the HALT signal here ...)

 

2. Do 400/800 NTSC machines run properly using 6502A CPUs?

 

Still open:

If anybody can provide hard facts and/or documents to clear up the fog...

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one thing to consider when thinking about atari 6502C

clock is not gone while halt is asserted, so you can't really tell without going all that trouble ijor made for Antic (decaping and microphotography for a start, ending up with schematics) if circuit is in static mode, or if its repeating last cycle internally

 

considering the fact that this is nmos logic part and limitations of this technology (need a clock >100khz or so, or it forgets what it suppose to do) i would say it repeats last cycle it executed with some internal logic disabled by one mean or the other

 

What are you talking about Sebastian? In the case of the 800 with a plain 6502B, the clock is actually stopped in the CPU pin. Of course that in the case of Sally it is not, because the logic that stops the clock on HALT is inside the chip (that's the whole purpose of Sally). But this doesn't matter for this purpose. You still have a 6502 core inside Sally, and the clock for that core is stopped on HALT. And even when it wouldn't be like that (which I bet it is), the behavior of a stopped clock is still valid for a 400/800.

 

So it can't be repeating the last cycle internally at all (this is more or less what happens with RDY, but not on HALT). It is just performing a very long cycle. The specifications for the minimum frequency are 50 KHz - 100 KHz (depending on which datasheet you look). But this formal specification is probably just a rough estimation. It is obvious that the CPU can work correctly with very long clock cycles.

 

Anyway ... decapping Sally is planned, but I think it is not a top priority.

 

Could it be that the 2 MHz failed Sally was repackaged as a 6507 for 2600s and disk drives?

Leave /HALT alone and it behaves just like a normal 6502, doesn't it?

 

Doesn't sound very likely. The 6507 die mask is not identical to the 6502 one (let alone to Sally). Using a 6502 (or Sally) die in a 6507 package would require a custom bonding, at the minimum to disable IRQ, NMI and HALT signals. I'm not sure that would be feasible.

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Or may be the guys who did the "slicing" of the chips (sorry, cannot remember the project page) will discover what is really inside Sally.

 

I guess that, eventually, we'll decap Sally. But probably we won't see anything very interesting in this regard.

 

How about topic 2? Did anybody give it a try?

...

2. Do 400/800 NTSC machines run properly using 6502A CPUs?

 

That's not a simple test to perform. Trying a single 6502A in a single computer won't tell you too much. Let's say it fails, so what? You would need several chips and several boards to get any confirmation. But chances that it won't fail, at least not just like that. Again, so what? You would need to test many chips, using many boards. You would need to find a "good" way to test the worst case software. And you would need to use worst PVT conditions as possible (apply heating, decrease voltage, etc).

 

Edit: corrected PVT/PVC typo.

Edited by ijor

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Or may be the guys who did the "slicing" of the chips (sorry, cannot remember the project page) will discover what is really inside Sally.

 

I guess that, eventually, we'll decap Sally. But probably we won't see anything very interesting in this regard.

 

How about topic 2? Did anybody give it a try?

...

2. Do 400/800 NTSC machines run properly using 6502A CPUs?

 

That's not a simple test to perform. Trying a single 6502A in a single computer won't tell you too much. Let's say it fails, so what? You would need several chips and several boards to get any confirmation. But chances that it won't fail, at least not just like that. Again, so what? You would need to test many chips, using many boards. You would need to find a "good" way to test the worst case software. And you would need to use worst PVT conditions as possible (apply heating, decrease voltage, etc).

 

Edit: corrected PVT/PVC typo.

 

 

Hey, that's nice to realize that you are doing the re-engineering - sorry I couldn't remember instantly. I just go from time to time to atariage.

 

What I like to overcome before I pass away is to get to know the facts about those cpu issues. Those what is it good for discussions, I feel a little bit tired with it, since they are going on for nearly three decades now. There is no proper documentation about this and I simply like to clearify and documents this. Bad or no documentation at all unfortunately is a constant with ATARI (see dadhacker blog) ...

 

Concerning the testing of 6502A CPUs in 400/800 you are totally right. Why: I've seen a dozend or more 400/800 NTSC from the inside and all were equipped with Bs. When collecting and verifying information for this project (www.abbuc.de -> see Profibuch for Download) I have been told by a few ATARIans, that "of course" they have or think there are 6502A CPUs in their 400/800s. But nobody delivered a proof. A lot of chat stuff, hot air and no facts. So I went to a wider auditorium to uprade chances and "advance bonus".

 

If this is all interesting ? Well, as Calvin once mentioned: "In a cosmic sense probably NIL!" ;)

 

Go for as party now - Happy New Year

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A quick search on ION implanted semiconductors does return a lot of results so I don't think it was just made up.

 

Every single 6502 has Ion implantation.

 

The process before that was ion diffusion - a gas of the dopant was allowed to cover the wafer under heat for a long period (usually hours) during which time it would gradually "soak" into the silicon. This resulted in heavier concentrations at the surface, with the concentration lessening as you got further into the silicon. This had certain negative affects on the quality of the IC.

 

It was eventually replaced by ion implantation - the dopant was "shot" into the wafer using strong electric fields instead of just being allowed to gradually diffuse into the surface. This would usually give a more constant concentration of the dopant by depth compared to diffusion. It also kept the dopant almost exactly under the mask where diffusion resulted in "smearing" as the dopant spread out from where it entered through the mask. This allowed for smaller feature sizes as well.

 

The switch-over from diffusion to implantation took a while, and was "big news" to people in the business, so it wasn't surprising that chip makers touted this for some time after switching. It's similar to how many TV shows touted "In color!" for a few seasons after the switch from black and white to color. Sure, EVERYONE was in color, but they still kept proclaiming it as if it were still new and unusual. :)

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Thank you to everybody for this vivid discussion here. So far it didn't lead to a qualified source, which somehow reminds me of some similar discussions during the last 25 years.

 

Topic 1 may be never unrevealed until some docs in the atari museum might be found ...

Or may be the guys who did the "slicing" of the chips (sorry, cannot remember the project page) will discover what is really inside Sally.

Topic 1 is superfluous... there's no possible interesting answer and "chopping" up the chip wouldn't ever answer that... what would answer that is Atari's own speed grading specifications for SALLY... the dies should be identical, regardless of speed grade. (again, there might have been some modifications made to higher speed bracket dies for specific reasons, but any such changes would likely eventually be applied across the board -the only reason it wouldn't be done immediately is if it cost more to do and was only absolutely necessary for higher speed operation... I have no idea if any such changes exsit and there's not any evidence that they do, but it was speculation on my part as to why Atari used the 6502B rather than the 2 MHz A unit -another reason could simply be that the B unit was in higher supply at the time and that both A and B rated chips were used in some machines)

 

How about topic 2? Did anybody give it a try?

 

So

 

1. So what is hidden in Sally - type A, B or C? (ehm, just to make it clear, it's not about the HALT signal here ...)

 

2. Do 400/800 NTSC machines run properly using 6502A CPUs?

 

Still open:

If anybody can provide hard facts and/or documents to clear up the fog...

Firstly you'd need to test a couple dozen machines and chips to get any viable results and chances are you wouldn't see any failures as such.

If, for whatever reason, Atari really did need 3 MHz rated chips, many, many 2 MHz (or even 1 MHz) rated chips may also have worked fine just as many, many chips can be overclocked without any problems.

Or the same reason that there were many cases of 3rd party vendors re-testing and re-grading CPUs into higher speed brackets using more precise testing until the primary manufactuers started offing those higher speeds at lower prices anyway. (though sometimes that never happened -like 68000 CPUs upwards of 20 MHz -and there were commercially regraded CPUs well above 25 MHz, or in cases where the chip really wasn't stable up to the next highest official speed grade, it could have been re-graded in-between, like a 14 MHz 68k, or 9 MHz, or a 1.5 MHz 6502, 1.8 MHz, 3.5 MHz, etc, etc)

And then beyond that, there's cases where the producer of the final product regrades the stuff themselves, or chooses to overclock it if they find that yields/failures are at acceptable levels.

 

 

 

 

Doesn't sound very likely. The 6507 die mask is not identical to the 6502 one (let alone to Sally). Using a 6502 (or Sally) die in a 6507 package would require a custom bonding, at the minimum to disable IRQ, NMI and HALT signals. I'm not sure that would be feasible.

Interesting, I thought the 6507 was identical to the 6502 internally, but just had missing external pins. (were the lines for the omitted address/irq/etc pins actually removed from the die of the 6507?)

I'd have though that unifying production would have saved cost. (the way a lot of modern CPUs are done as such -using simialr dies with removed external functionality or lower pin count packages for lower price brackets)

 

Was the 6507 used by Atari rated at 1.5 MHz or something, or did Atari find overclocking acceptably reliable? (1.19 MHz seems like overclocking for a 1 MHz part -enough to make others resort to 895 kHz when dividing from a 3.58 MHz master clock)

 

 

 

Valid point there (2).

 

Wouldn't a 6502 out of a VIC-20 be good candidate for testing that one?

That wouldn't have been a 6502A, would it? (rather a 1 MHz rated part -assuming they didn't occasionally use higher rated parts when supply favored it) So you might get some failures in testing actually due to CPU instability at the normal 1.79 MHz rather than something else necessitating a 3 MHz 6502B. (some would probably work fine, but you'd probably eventually get one that didn't like being overclocked)

 

 

 

On another note:

does anyone know if there were ever commercially manufactured NMOS 6502Cs (ie 4 MHz grade) or if that was just formally reserved for a 4 MHz part that never ended up being sold? (by MOS or otherwise)

Edited by kool kitty89

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Interesting, I thought the 6507 was identical to the 6502 internally, but just had missing external pins. (were the lines for the omitted address/irq/etc pins actually removed from the die of the 6507?)

I'd have though that unifying production would have saved cost. (the way a lot of modern CPUs are done as such -using simialr dies with removed external functionality or lower pin count packages for lower price brackets)

 

Yes, it is natural to avoid making yet another mask, but sometimes you can't help it. And because the mask is a once only, non-recurring cost, it is not too significant for a mass produced die as the 6507. They also try when possible, to modify a single (or nowadays, as few as possible) metal layer.

 

In this case, the mask has to be different because otherwise the IRQ and NMI input signals would be left floating. The CPU couldn't work like that. The missing output signals, such as the higher Address lines, is not important for this purpose.

 

does anyone know if there were ever commercially manufactured NMOS 6502Cs (ie 4 MHz grade) or if that was just formally reserved for a 4 MHz part that never ended up being sold? (by MOS or otherwise)

 

As I said above, seems it was produced but it is rare, there are a few pictures available online. I think even a couple of pictures were posted here sometime ago.

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the real core of the 6502....I guess it has to be motorola, since the principle designers, mensch and peddle left motorola to set up mos's processor division (since mos were still existing)

 

so, there's a bit of Motorola know how in a 6502 or any mos/cbm processor product

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does anyone know if there were ever commercially manufactured NMOS 6502Cs (ie 4 MHz grade) or if that was just formally reserved for a 4 MHz part that never ended up being sold? (by MOS or otherwise)

 

As I said above, seems it was produced but it is rare, there are a few pictures available online. I think even a couple of pictures were posted here sometime ago.

 

It's a bit odd that faster 6502s weren't used more often... even if the 4 MHz version was expensive (due to low yields), the 6502B seems to have been pretty common. Then again, there's plenty of designs that took an excessively long time to upgrade from 1 MHz anyway, or others that started off at 1 MHz rather late (like the C64). The Apple II in particular is odd that way in waiting until the II+ to go beyond 1 MHz (they switched to a 6502C before a faster 6502...), especially odd as faster DRAM should have been relatively affordable much sooner than that. (at least enough to allow 2 MHz... or even earlier than that and/or higher speeds if they'd modified the DMA mechanism to allow full non-interleaved bus access to the CPU with wait states enforced when video needed to access the bus -for that latter case they could have used a 2 MHz 6502 with the same bus speed as the 1 MHz Apple IIs -more than that without faster RAM would be a somewhat moot since the 6502 doesn't do much work off the bus compared to some other CPUs -Z80, 68k, x86, etc)

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Hello guys

 

I just remembered that one of the 6502 versions might be in the old (1987) Maplin Electronics catalog I have. Of the 6502 family, only the 6502A is mentioned:

 

6502A Microprocessor

 

An 8-bit microprocessor in a 40pin DIL package. The device requires only one +5V supply and the bus is directly compatible with the MC6800 series IC's. The IC can address up to 64K bytes of memory with its 16-bit address lines. There are 13 addressing modes, 56 instructions and 7 internal registers. The 6502A requires a single phase TTL clock operating from a 2MHz crystal.

 

Hope that helps.

 

sincerely

 

Mathy

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http://www.visual6502.org/

 

These guys decapped a 6502 and built an animated model of it that can be stepped in javascript. They say their next projects are the TIA and RIOT from the 2600.

I knew about this 6502 simulation. Awesome news that TIA and RIOT are next. It would be even cooler if GTIA, ANTIC, and PoKey get done.

 

I wonder if tools exist for others to work on some chips? Especially with the decapping / schematics out there for the A8 chips.

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http://www.visual6502.org/

 

These guys decapped a 6502 and built an animated model of it that can be stepped in javascript. They say their next projects are the TIA and RIOT from the 2600.

Didn't Curt already have to do that for TIA and RIOT in the ASIC in the Flashback II?

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http://www.visual6502.org/

These guys decapped a 6502 and built an animated model of it that can be stepped in javascript. They say their next projects are the TIA and RIOT from the 2600.

 

They completed TIA, but it is still not public yet. Note btw, that original schematics for TIA are available here in Atariage. They didn't complete RIOT, but only partially to be able to boot a "virtual" 2600. Next on their line is probably Z80.

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After reading this entire thread, I noticed you guys are constantly talking about Sally as the 6502C. This is not correct. Sally is a 6502c. <--- Lower case, guys! You really have to be accurate about this. It's kept this thread going on about speed designations for so long, when it's not even an issue. It's irrelevant to Sally's designation. The lower case c does however stand for "custom".

 

For what I know about the internals, Atari got the license from Rockwell to use it's design, and they added the /Halt logic, also buffering the address and data buses so it'll go into "High Z" or high-impedance mode when halted. This makes it possible for Antic to take over those buses fully. The dynamic ram inside the Atari will never fail to be refreshed, since Antic is responsible for what's known as CAS-only refreshing of the RAM. There is ALWAYS one processor (yes, Antic is a processor too) using the buses inside the Atari. Basically, Sally is the Slave processor of Antic in this case, since Antic dictates when Sally may use the buses.

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After reading this entire thread, I noticed you guys are constantly talking about Sally as the 6502C. This is not correct. Sally is a 6502c. <--- Lower case, guys! You really have to be accurate about this. It's kept this thread going on about speed designations for so long, when it's not even an issue. It's irrelevant to Sally's designation. The lower case c does however stand for "custom".

 

Atari themselves used the uppercase designation:

http://www.atarimuseum.com/computers/8bits/xl/xlspecs/600xlspecs.JPG

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After reading this entire thread, I noticed you guys are constantly talking about Sally as the 6502C. This is not correct. Sally is a 6502c. <--- Lower case, guys! You really have to be accurate about this. It's kept this thread going on about speed designations for so long, when it's not even an issue. It's irrelevant to Sally's designation. The lower case c does however stand for "custom".

 

Atari themselves used the uppercase designation:

http://www.atarimuseum.com/computers/8bits/xl/xlspecs/600xlspecs.JPG

 

But in the same document they have written "ANTIC( .. controlls input/output) :)

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There's more errors in that sheet than I dare count. But no matter what that one sheet says, other official documents do it right, although even they used upper case at times. Some people just don't take care about such seeming trivialities, and back then, the 6502C wasn't even made yet, so it didn't really matter. Just goes to show how such a small thing as letter case, matters in technical things. People been talking on about speed, and it never even was relevant to the question.

 

<reason for edit: I read the date wrong and said this was an issue for a year, but it's only 2 weeks, kinda. lol But the thread was long enough to have taken over a year. ;-) >

Edited by Alphasys

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lol But the thread was long enough to have taken over a year. ;-) >

You must not have seen any year-long thread topics on AA... this pales in comparison to say the least. :P

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