How to fix refresh problems DRAM

[HiassofT]

Hi Marius!

 

I do another test. It is quite simple. I fill the complete extended memory with a certain value. I start using my atari with 64KB software, so the extended memory is not used. Then I run my own 'check memory' tool. As soon as a "*" is printed on the screen the memory is different from the value it should be.

 

I found out years ago that as soon as the 'screen is off' (the make your atari 30% faster 'trick') the memory problem occurs even sooner.

I wrote a similar test (turning the screen off) some 15 or 20 years ago, to test the refresh problems of my 1MB simm upgrade :-)

 

You also could disable DMA, IRQs and NMIs and then let the CPU spin in a tight loop. For example something like this:

     LDA #4
WAIT BIT 53279
    BNE WAIT

This minimizes DRAM access and should show refresh errors even faster.

 

But it's also a good idea to combine these tests with the conventional memory testers, especially those checking for timing issues (PAGEFIND.BAS and Numen). When messing with DRAM timing (as the CAS mod does) there's a slight chance something will fail, for example the DRAM access immediately after the refresh cycle.

 

one DRAM I'm 100% sure it has this problem is:

 

MB81C4256A-70P

I found a short datasheet and it mentions the chip supports RAS only, CAS-before-RAS and hidden refresh. It didn't contain detailled timing information though. So: just try the mod :-)

 

so long,

 

Hias

[ClausB]

Also check whether your DRAMs need 8 bits refresh address or 9.

The MB81C4256A datasheet says "512 refresh cycles every 8.2 ms". That's 9 bits, too many for any ANTIC. Either add a circuit to generate a ninth bit or try the CAS-before RAS mode.

[Marius]

The MB81C4256A datasheet says "512 refresh cycles every 8.2 ms". That's 9 bits, too many for any ANTIC. Either add a circuit to generate a ninth bit or try the CAS-before RAS mode.

 

Three questions about this:

 

1. Can you conclude that '512 refresh cycles every 8.2ms' means, it is 9 bits... or is the '9bits' thing mentionned beside that information in the data sheet? (I don't understand how you get to '9 bits' from the info: 512 r.cycles (sorry, this is rather new for me)

 

2. How can I create a circuit that generates a 9th bit?

 

3. Is the reason that my memory expansion kept losing data, due to this 9bit thing?

 

Thanks

Marius

[MEtalGuy66]

The MB81C4256A datasheet says "512 refresh cycles every 8.2 ms". That's 9 bits, too many for any ANTIC. Either add a circuit to generate a ninth bit or try the CAS-before RAS mode.

 

Three questions about this:

 

1. Can you conclude that '512 refresh cycles every 8.2ms' means, it is 9 bits... or is the '9bits' thing mentionned beside that information in the data sheet? (I don't understand how you get to '9 bits' from the info: 512 r.cycles (sorry, this is rather new for me)

 

2. How can I create a circuit that generates a 9th bit?

 

3. Is the reason that my memory expansion kept losing data, due to this 9bit thing?

 

Thanks

Marius

 

It shouldnt be..

 

If the dram has 9-bits of adressing, it (usually) only requires 8-bits of refresh adressing..

(the rows are refreshed 2 at a time)

 

With 256k, you need 8-bits..

Edited February 13, 2011 by MEtalGuy66

[ClausB]

The MB81C4256A datasheet says "512 refresh cycles every 8.2 ms". That's 9 bits, too many for any ANTIC. Either add a circuit to generate a ninth bit or try the CAS-before RAS mode.

 

Three questions about this:

 

1. Can you conclude that '512 refresh cycles every 8.2ms' means, it is 9 bits... or is the '9bits' thing mentionned beside that information in the data sheet? (I don't understand how you get to '9 bits' from the info: 512 r.cycles (sorry, this is rather new for me)

 

2. How can I create a circuit that generates a 9th bit?

 

3. Is the reason that my memory expansion kept losing data, due to this 9bit thing?

 

Thanks

Marius

1. Yes, 512 is 2 to the 9th power. Here's the datasheet.

 

2. That's probably more complicated than the CAS-before-RAS circuit. In my 256K upgrade for the 800XL, I used an 8-bit counter to add an 8th refresh bit to ANTICs with only 7 bits.

 

3. Probably. Theoretically, half of your expansion should get refreshed and the other half will forget after a short while (although normal RAM accesses will also refresh some RAM).

[ClausB]

With 256k, you need 8-bits..

Not with this chip. It's a 1 Mb DRAM, 256Kx4. Look at the datasheet above.

Edited February 13, 2011 by ClausB