Geneve 2 Phoenix?

[+9640News]

He's still working on it.

 

This from the 8th August:

 

"Things are going well. Too busy at work as always but it makes the days pass.

 

The Geneve II FPGA programming issue is solved. I had to go onto the Altera forums and spend a lot of time to fix this but it is only a small mod to the pcb so easily doable.

 

I have also tried to get the 9995 into the first FPGA and it is almost there from a timing point of view. To begin with the system failed by 120 ns and after a week or two hacking the design and telling the Altera tool about the expected timing it is down to failing by 8 ns. This 8 ns is down to me trying to be smart ( should have known better ). I am trying to find out if a dram access is required in 5 ns from the 9995 setting the address bus and this is taking 13 ns presently so I will have to try some design optimisation etc to get this working. If I can sort this then the Altera tool recons that the DDR will be 144MHz and the 9995 core ( 16 bit interfaces ) will be 72MHz which is what I was designing for."

 

Any idea if the 9995 was implemented in the MIST FPGA?

Beery

[patrickmcmichael]

What ever became of this initiative?

[Shift838]

I have reached out to the developer (Gary) a few times in the last year, most recent a couple of months ago. I have not heard of an update as of yet. As soon as I do I will post here.

 

However, Gary did send me all the code he used to develop this as the design is on a FPGA board and gave me permission to see if I could port it to the MiST. I need to find it, maybe it could be adapted for use on the MiSTer FPGA system.

Edited June 6, 2019 by Shift838

[patrickmcmichael]

I have reached out to the developer (Gary) a few times in the last year, most recent a couple of months ago. I have not heard of an update as of yet. As soon as I do I will post here.

 

However, Gary did send me all the code he used to develop this as the design is on a FPGA board and gave me permission to see if I could port it to the MiST. I need to find it, maybe it could be adapted for use on the MiSTer FPGA system.

 

What is the MiST ?

[Shift838]

 

What is the MiST ?

The Mist is a FPGA system that simulates retro systems hardware

 

The newest FPGA out that has development happening Constantly is the Mister FPGA. This is a DE-NANO-10 based system.

 

Google MiSTer FPGA.

 

https://github.com/MiSTer-devel/Main_MiSTer/wiki

[+9640News]

On 6/5/2019 at 10:12 PM, Shift838 said:

I have reached out to the developer (Gary) a few times in the last year, most recent a couple of months ago. I have not heard of an update as of yet. As soon as I do I will post here.

 

However, Gary did send me all the code he used to develop this as the design is on a FPGA board and gave me permission to see if I could port it to the MiST. I need to find it, maybe it could be adapted for use on the MiSTer FPGA system.

Just looking to see if you ever found the code and what became of it.  Might be good to have for historical reasons.

Beery