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VDP Block Diagram & limit of using an emulator


F-Cycles

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I have started to look to the video chip and especially the VDP Block Diagram. I don't have a real hardware and my tests are limited to be running in BlueMSX.

 

So far, my test show that a single sprite can have a different color per scan line and a single sprite can be 16 pixels by 192. But that's not that interesting with the 32 sprites already available... unless to show a screen with 48 sprites - did anyone had ever done it? - (since 192 pixels height is 12 sprites and 4 sprites per line x 12 sprites = 48 sprites on screen).

 

 

In fact, all values seem to be stored for each scan line...

 

Which I am not sure it's the case on the real hardware for all values!? Because the VDP has 8 internal registers. Some of these registers may be connected directly to other gates to produce the desired results... That's my guess so far. I target especially the register which magnify the sprites (which does not need to read any values from the RAM to be effective). This bit could be directly connected via a line to a logic gate and as soon the bit toggle, it may produce a change in the circuitry...

 

in my test, I place 2 sprites one on the left side of the screen and one on the right side of the screen. The distance between the two was $D0 which is 208 pixels... which give about 138.6 T (CPU) clocks in between the two (enough for the few instructions needed). I then attack the register 1 toggling the bit. The result is that I see one scan line show the 2 sprites magnify by 1x and next scan line magnify by 2x and so on (few scanline has double 1x or 2x), as I did not try to be in sync with the HSYNC.

 

I pause the emulator a couple of time and never notice for the same scan line a different result for the 2 sprites.

 

I would like to know if someone has done some research about that MAG bit or the SIZE bit?

 

Thanks

Best Regards,

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