New homebrew board coming soon...

[CPUWIZ]

Happy T'Day everyone,

 

here is something I cooked up with RevEng (bBasic support will come). It's a board that can handle 27C128, 27C256, 27C512, 27C010 and 27C020 EPROM's and it uses a 22V10 PLD to do the bankswitching (sorry, no 20V8 and not backward compatible with any other board). Every single pin on the PLD is used for 256K, so even if you have a suggestion, it's too late. It also supports SARA chips, so in essence, it's a 10 in 1. Two new bankswitching schemes have been designed, RevEng already has a locally hacked copy of Stella (once flushed out, Stephena will likely put it into the official version).

 

So, bankswitching:

 

F4, F4SC, F6, F6SC, EF, EFSC, DF, DFSC, BF and BFSC.

 

DF/DFSC is the new 128K bankswitching scheme, touch $1FC0 to $1FDF to select 32 banks.

BF/BFSC is the new 256K bankswitching scheme, touch $1F80 to $1FBF to select 64 banks.

 

Here are a couple pics, both of the routed new board and my hacked up SARA board to deal with all the above mentioned methods (currently configured to 256K, no SARA).

 

[rjchamp3]

What will this cost interesting

[Thomas Jentzsch]

For those who are no hardware experts (like me), maybe you could list the advantages of the new board?

 

Thanks!

[CPUWIZ]

The advantage of the board to me, is the fact that someone asked me if I could pull off SARA + 128K bankswitched. I pondered on it, figured that if I am gonna route a new board, I might as well make it versatile.

 

Don't make me translate that into German, please.

[AtariLeaf]

Der Vorteil des Boards zu mir, ist die Tatsache, dass jemand fragte mich, ob ich SARA + 128K bankswitched abziehen. Ich dachte darauf dachte, wenn ich werde Route ein neuer Vorstand, ich könnte genauso gut es vielseitig zu machen.

Lassen Sie mich nicht, dass ins Deutsche zu übersetzen, bitte.

 

Lets see if Thomas can make that out

[Andrew Davie]

Happy T'Day everyone,

 

here is something I cooked up with RevEng (bBasic support will come). It's a board that can handle 27C128, 27C256, 27C512, 27C010 and 27C020 EPROM's and it uses a 22V10 PLD to do the bankswitching (sorry, no 20V8 and not backward compatible with any other board). Every single pin on the PLD is used for 256K, so even if you have a suggestion, it's too late. It also supports SARA chips, so in essence, it's a 10 in 1. Two new bankswitching schemes have been designed, RevEng already has a locally hacked copy of Stella (once flushed out, Stephena will likely put it into the official version).

 

So, bankswitching:

 

F4, F4SC, F6, F6SC, EF, EFSC, DF, DFSC, BF and BFSC.

 

DF/DFSC is the new 128K bankswitching scheme, touch $1FC0 to $1FDF to select 32 banks.

BF/BFSC is the new 256K bankswitching scheme, touch $1F80 to $1FBF to select 64 banks.

 

Here are a couple pics, both of the routed new board and my hacked up SARA board to deal with all the above mentioned methods (currently configured to 256K, no SARA).

 

 

Onboard RAM?

[CPUWIZ]

No, C020231, SARA.

[+Gemintronic]

I now can make 4 way scrolling games. The maps to eat up quite alot of space. If I'm ever going to make an Ultima style game this would be the thing that makes it happen (with RevEngs support ~_^ )

 

Wasn't there some guy who was selling his collection of SARA donor carts? Whatever happened to that?

[Mr SQL]

No, C020231, SARA.

Can it support RAM Plus the same way?

[Thomas Jentzsch]

 

Lets see if Thomas can make that out

 

I suppose CPUWIZ couldn't do any better.

[Wickeycolumbus]

Always good to see new hardware get mass produced. Interested to see what people come up with now!

 

Let us know when it's available, I'd definitely be interested in a board or two to play with.

[CPUWIZ]

I suppose CPUWIZ couldn't do any better.

 

LOL, sehr witzig.

[+Gemintronic]

Wasn't there some guy who was selling his collection of SARA donor carts? Whatever happened to that?

 

I guess my secret question was: would I need to find donor carts to add SARA to my games using these awesome 256k boards or are you set?

[CPUWIZ]

Bumping an old thread, with a new picture. This is revision A, it has one bug (minor and already fixed), so I need to run another. But it works well.

 

 

[Wickeycolumbus]

Cool!

 

Will this board support batari's superbanking? If you're unfamiliar, superbanking has 4K banks but it's hotspots are in the $0800 range, so you don't have to waste ROM for them.

[CPUWIZ]

Cool!

 

Will this board support batari's superbanking? If you're unfamiliar, superbanking has 4K banks but it's hotspots are in the $0800 range, so you don't have to waste ROM for them.

 

Maybe, I need more details please. What is the exact spec?

[Wickeycolumbus]

 

Maybe, I need more details please. What is the exact spec?

 

 

From kevtris's mapper doc:

 

 

SB (Superbanking)-----This is the same as 0840, except A0-A6 are used instead of just A6, as so:A13           A0----------------0 1xxx xBBB BBBBBy using 6 bits, the maximum ROM size has been increased from 8K to 256K.

 

Also, these posts in batari's blog:

 

http://atariage.com/forums/blog/134/entry-3979-supersize-me/

http://atariage.com/forums/blog/134/entry-4239-512k-superbanking-with-ttl/

[+iesposta]

So that is a superchip? Wow.

I always imagined them smaller, like the size of an LSxxxx.

 

You gotta stop making them colored and cleanly designed, because I want them in a clear lighted shell!

How about a run of clear epoxy or resin bricks (where you could still remove the EPROM. Probably way too expensive, but for limited editions...

[CPUWIZ]

So that is a superchip? Wow.

I always imagined them smaller, like the size of an LSxxxx.

 

You gotta stop making them colored and cleanly designed, because I want them in a clear lighted shell!

How about a run of clear epoxy or resin bricks (where you could still remove the EPROM. Probably way too expensive, but for limited editions...

 

Haha, yep the SARA chip is the same size as a 2732 EPROM. CommaVid used 2 x 1K x 4 chips in Videolife and MagiCard, those are about the size of a 74XXX.

 

At the moment, I don't see any reason why SuperBanking wouldn't work, at least without the SARA chip. I am not exactly sure how it would behave, since it captures the low address lines for the read/write window and all address lines are connected to it.

[Wickeycolumbus]

 

Haha, yep the SARA chip is the same size as a 2732 EPROM. CommaVid used 2 x 1K x 4 chips in Videolife and MagiCard, those are about the size of a 74XXX.

 

At the moment, I don't see any reason why SuperBanking wouldn't work, at least without the SARA chip. I am not exactly sure how it would behave, since it captures the low address lines for the read/write window and all address lines are connected to it.

 

Good to hear. Let us know if you try it out.

[CPUWIZ]

Me and RevEng tried a few different SuperBank methods this evening. The one that I can make work, is LDA $0880-$08BF, no STA!

 

We have a working demo of "my" SuperBanking in progress, without wasting 64 bytes per bank. This can be dialed back all the way to 16K (or previously known as F6).

 

 

P.S. SARA is a no go on this method, the chip prevents it somehow, have not dug into it deeper, other than theory I shared with RevEng. Still though, no board change needed and 64 x 4K banks works, without a single byte of ROM space wasted.

[+batari]

DF/DFSC is the new 128K bankswitching scheme, touch $1FC0 to $1FDF to select 32 banks.

BF/BFSC is the new 256K bankswitching scheme, touch $1F80 to $1FBF to select 64 banks.

DF/BF with/without SARA are officially working on Encore. What threw me for a long time was that I assumed BF was 1FB0-1FEF and DF was 1FD0-1FEF until I actually *read* the above

 

But that makes me wonder, why waste 16-48 bytes? The 22v10 should be able to handle that higher address range. It might require an extra product term or two in the address decode logic for that pin you run to the clock line but it should work (I think the 22v10 allows at least eight product terms per output pin.)

[CPUWIZ]

DF/BF with/without SARA are officially working on Encore. What threw me for a long time was that I assumed BF was 1FB0-1FEF and DF was 1FD0-1FEF until I actually *read* the above

 

But that makes me wonder, why waste 16-48 bytes? The 22v10 should be able to handle that higher address range. It might require an extra product term or two in the address decode logic for that pin you run to the clock line but it should work (I think the 22v10 allows at least eight product terms per output pin.)

 

 

Me and RevEng tried a few different SuperBank methods this evening. The one that I can make work, is LDA $0880-$08BF, no STA!

 

We have a working demo of "my" SuperBanking in progress, without wasting 64 bytes per bank. This can be dialed back all the way to 16K (or previously known as F6).

 

 

P.S. SARA is a no go on this method, the chip prevents it somehow, have not dug into it deeper, other than theory I shared with RevEng. Still though, no board change needed and 64 x 4K banks works, without a single byte of ROM space wasted.

 

You did see the post above yours, yes?

[Cybearg]

Anything new on this front?

[CPUWIZ]

Due to lack of interest, I never re-submitted the fixed boards to my manufacturer. I sit on too many things already, like 100 of these.