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alex_79

Question: 7800 memory map in 2600 mode

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I modded my 7800 by installing the DevOS 0.2 bios and built the parallel cable adapter. I tested it under dosemu in linux and I successfully dumped carts and used the "Tia Sound Editor", so the connection works fine. I'm waiting for some cheap sram ic that I bought online and should arrive in a few days so I can build a ram cart.

I will use the 7800 for 2600 developement and I plan to build the 32K linear cart first.
The cart is mapped from $8000 to $FFFF. I know I can safely use the addresses with A12 bit set in 2600 mode, that result in 16k ram mapped as follows:

$9000-$9FFF
$B000-$BFFF
$D000-$DFFF
$F000-$FFFF

By looking at the schematic for the 32K ramcart, the ram is also selected when A12 is LOW, so the question is: does the 7800 (in 2600 mode) mirror TIA and RIOT registers in every memory addresses with A12 LOW, like it happens in a 2600 console?

If it does, use of the other half of the 32k linear cart in 2600 mode ($8000-$8FFF, $A000-$AFFF, $C000-$CFFF and $E000-$EFFF) would cause bus contention and should be avoided, else if TIA and RIOT are only mapped in the lower addresses, the entire 32K area ($8000-$FFFF) would be available also in 2600 mode.



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You should't be able to access any more than the first 4k in the ramcart in 2600 mode. In 2600 mode A12->A15 aren't available (follow them from the 6502 or cart connector on the 7800 schematic) so you won't be able to get higher than 4k. The 6502 may ask for more internally, but that's not substantially different than what happens on the 6507 with its missing A12-A15 lines.

 

AFAIK the TIA and RIOT registers are mirrored the same as the 2600, when in 2600 mode. I have heard tell that there are games that use those mirrors instead of the base addresses. I'd expect those games to break rather spectacularly if they weren't.

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I looked at the schematics and it seems that the CPU (U2) A0-A11 and A13 are directly connected to the cart port (J1), while A12,A14 and A15 are ANDed with the /CE signal from the BIOS ROM (U7) before going to the cart. So I think that when the cart is selected it can see all the address bus. Of course a 2600 cart doesn't have the pins corresponding to A13,A14 and A15, but the ramcart is on a 7800 board, so all the signals are there.

post-10599-0-45915300-1426514200_thumb.jpg

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I'm no expert at reading schematics, but U11 is a flip flop with reset. I'm assuming its used as a latch for 2600 mode. Without output from U11-10, the AND gates for the higher lines will never pass signal to the cart port. No?

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I'm no expert at reading schematics

Neither am I, but that flip-flop output is also connected to \CE on the BIOS ROM (U7): when it is LOW the BIOS is mapped to $8000-$FFFF (the other CS pin is tied to A15), so it must be HIGH to access the cart in both 7800 and 2600 mode and in that case the high addresses are indeed passed to the cart port.

 

I checked the RIOT and TIA connections on the 2600 and 7800 schematics, and there are only two differences:

 

- RIOT pin 37 (an active LOW chip select pin) is tied to A12 on the 2600 and to \6532CS (Maria pin 23) on the 7800

post-10599-0-03217600-1426519404_thumb.jpg

 

- TIA pin 22 (active LOW chip select pin) is tied to ground on the 2600 and to \TIACS (Maria pin 26) on the 7800

post-10599-0-47883100-1426519402_thumb.jpg

 

So it all depends on how those two Maria pins behave in 2600 mode.

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After a bit o research, I found this (it's from the 10/1984 Maria Specs document that you can find here):
post-10599-0-29492300-1426521298_thumb.jpeg
So the memory map is the same as in the 2600, which means that addresses $8xxx, $Axxx, $Cxxx and $Exxx, when using a 32K ramcart in 2600 mode, are mapped to BOTH the cart and the TIA/RIOT and must not be used to avoid bus contention.

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I have a few 8K sram chips so, while I'm waiting for the bigger ones to arrive, I built a 16K cart that is only mapped in the address range used in 2600 mode. I used a Pole Position II cart which have pin 1 and 32 unconnected. It was a bit tricky but I finally managed to add the required connection while still allowing the cart to be plugged in the cart port without modification.
post-10599-0-18783900-1426586141_thumb.jpgpost-10599-0-42943600-1426586137_thumb.jpg
I tested it by creating 4k,8k,12k or 16k rom (using the org/rorg statements in dasm to assemble with the correct addresses) then I uploaded the binary using the "-d" option which doubles every 4k "bank". It works perfectly! A12 is used as chip select, so there's no bus contention in 2600 mode. Here's the schematic using 2 8k sram chips and a 74LS00.

post-10599-0-47483200-1426586117_thumb.jpg


The 48K ramcart design can be modified in the same way to obtain a 24K cart mapped as follows:

$5000-$5FFF
$7000-$7FFF
$9000-$9FFF
$B000-$BFFF
$D000-$DFFF
$F000-$FFFF

It makes sense to build one of these if you only need 2600 mode and have small sram chips lying around.

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