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Hi-Res Bally Arcade/Astrocade Correspondence

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Michael updated me again on March 25, 2019.

Here are Michael's comments:

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I indicated I would email you when I have something positive to report to you. I wired up the quick-connect breadboard starting off with the standard motherboard chips scheme U22 and U21 for the RAS and CAS (both active low) RAM timing lines. This was my preliminary first test for correct wiring operation. The low-res menu and Checkmate ran nearly perfect, which was a good start for this breadboard idea of mine. Just for the heck of it, I decided to wire up the hi-res serial feed TV display circuitry with the simulated 3 static RAM chips as I indicated previously, just to see how this standard timing scheme would operate in the hi-res mode.

I first ran my simple hi-res SetScreen and Z80 halt routine. The hi-res TV display ran perfectly with NO flickering of pixels or bytes. I was really surprised. I then ran my "write only" Screen Fill routine and there was just one hi-res pixel at 4000H that was flickering. These two experiments are indicating that my latest static RAM scheme is a good scheme. The scheme needs to be tweeked. The timing may need to be adjusted and/or a series resistor may need to be inserted/adjusted. Pull-up resistors may not help. I plan to use my logic analyzer to take some measurements with this hi-res test and also on a standard perfectly working motherboard for comparisons.

Today's 2 tests in hi-res are indicating to me that there is a very good chance that the custom address and data chips can indeed operate in hi-res using 4 static RAM chips if one can get the timing right and the degradation down. I am still hoping for success with this project.

Bye.
MCM

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Michael's progress is moving along faster than I expected to see. That's great!

Adam

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I added "BalcheckHR User Manual - Scans" by Michael Matte from December 2018.

This 32MB pdf document contains 23 pages of handwritten notes, schematics, and board layouts for the BalCheckHR. These scans supplement the BalCheckHR User Manual. You can download it here:

http://www.ballyalley.com/documentation/BallyCheck/BallyCheck.html#BalcheckHRUserManualScans

Among the documents in these handwritten scans are:

  1. SetScreen3 Initial Display
  2. BalCheckHR Board
  3. BalCheckHR Board - EEPROM Interface
  4. DualBalCheckHR Board - Display
  5. BalCheckHR Board - Power Line
  6. Bally/Astrocade Motherboard - ROM Decoding
  7. Bally/Astrocade Motherboard - RAM Timing
  8. Bally/Astrocade Motherboard - Microcycler
  9. Bally/Astrocade Motherboard - Custom Address/Data
  10. Bally/Astrocade Motherboard - RAM Decouplers
  11. Bally/Astrocade Motherboard - Detailed Motherboard Layout
  12. Bally/Astrocade Motherboard - Notes
  13. Balcheck RAM Test Flow Chart
  14. BalcheckHR in a Cartridge
  15. Factory Tests
  16. Hi-Res Demo Magic Writes

Hardware gurus will find plenty to sink their teeth into here! Have fun, and report back with what you find!

Other BalCheckHR updates:

1) BalCheckHR Manual - This has not been uploaded anyplace yet. I'll do that this week.

2) BalCheckHR Software - The 32K EEPROM on the BalCheckHR has been dumped, though it also isn't available yet. The nearly 200-pages of handwritten Z80 source code for the BalCheckHR software has been photocopied, but Michael hasn't sent it to me yet.

When all of the BalCheckHR information is online, then all of the documentation required to build your own BalCheckHR and use it will be available.

Adam

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I added Michael Matte's "BalcheckHR User Manual" from from December 2018:

http://www.ballyalley.com/documentation/BallyCheck/BallyCheck.html#BalcheckHRUserManual

For ease of use with future updates to this manual, all documents are separate text files. Altogether, this manual is 85 pages long. It is made up of 17 different documents. They look best when printed with left and right columns of .8 or less using the 10 pt Courier New font.

Make sure to download the handwritten scans for this manual too, as together they are the complete BalCheckHR manual.

The complete manual is made up of a "Read First" file plus these 16 documents:

  1. BalcheckHR Introduction
  2. Keypad Usage
  3. Set Up
  4. Blank Power On
  5. Reducing RF Interference
  6. BalcheckHR Performance Check
  7. Standard Balcheck Tests
  8. Error Reports
  9. Balcheck Optional Programs
  10. More Options
  11. SetScreen3
  12. Optional Troubleshooting Programs
  13. High Resolution
  14. Doc References
  15. Miscellaneous Text Docs
  16. Miscellaneous Scans

Now I just have to confirm that the 32K EEPROM from the BalCheckHR was dumped correctly. If so, then someone can build their own BalCheckHR.

Adam

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BalCheckHR Pictures and screenshots for Bally Arcade and Astrocade
by Michael Matte (MCM)

I added 48 pictures of the BalcheckHR hardware along with screen shots of the device working. These were sent to me on January 29, 2019. You can view them on Archive.org, here:

https://archive.org/details/BalCheckHRPicturesandScreenshotsBallyArcadeAstrocade

MCM created the a new version of the BalCheck hardware called BalCheckHR for the Bally Arcade/Astrocade. These are pictures of the hardware and some screenshots of the software running. The pictures of Pixel Stringer are running on the Astrocade in Hi-Res mode-- a 320x204 pixel mode that he modified his astrocade to run on his hardware.

Here are the details he wrote to me when he sent me these pictures:

Well, here they are. The screen shots look pretty good to me. I'm sending a 2nd email with the Pixel Stringer photos. Most of the photos have a label to the left of the screen telling you what you're looking at. Hope you like them.

Here are the many photos for the Pixel Stringer. Unfortunately, my camera couldn't capture what I see when I run this demo on my 20" Toshiba CRT. The clarity and color is just not in the photos. Plus you are only getting a freeze frame of each 16 sec show. Half the fun is watching the pixel string move and grow. Sometimes the string moves really fast and sometimes slowly. That's part of the entertainment. Seeing the variations in the program. It's up to you which photos you would like to post. There are a bunch of them. If I can get that video to play on my desktop, that will be more fun watching the demo in action. But, this group of photos will give you an idea what this demo will display graphics wise.

Here are helpful link:

BalCheckHR User Manual:

http://www.ballyalley.com/documentation/BallyCheck/BallyCheck.html#BalcheckHRUserManual

BalCheckHR Handwritten Scans:

http://www.ballyalley.com/documentation/BallyCheck/BallyCheck.html#BalcheckHRUserManualScans

Nice!

Adam

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I added the BalCheckHR 8K ROM Image and the Z80 source code to BallyAlley.com.

1) BalCheckHR (ROM Image)
By MCM Design (Michael Matte).
2019.

This is the 8K ROM image for the software for the BalCheckHR unit. This hardware allows experienced electronics users to diagnose many problems with a Bally Arcade/Astrocade game console. This device has many improvements over the original BalCheckHR hardware, including special routines to test Astrocade units that have been modified to use high-res mode. On the BalCheckHR hardware, this is bank 0 of the 32K ROM on the BalCheck hardware. This programs requires a keypad overlay, which is described in the user manual.

http://www.ballyalley.com/emulation/cart_images/cart_images.html#BalCheckHRAstrocadeROMImage

2) BalCheckHR (Z80 Assembly Language Source Code)
By MCM Design (Michael Matte).
2019.

This is about 180 pages of handwritten, Z80 assembly language software for the BalCheckHR unit.

http://www.ballyalley.com/ml/ml_source/ml_source.html#BalCheckHRZ80SourceCode

The above two links also have links to the BalCheck manuals and scans. I think all of the information required to build your own BalCheckHR is now available. The BalCheckHR ROM image is the last piece of the puzzle to get everything required to use this diagnostic hardware/software combination.

The BalCheckHR also has two other pieces of software on the 32K EEPROM on the hardware:

Bank 1 - Remote ROM - A slightly modified on-board ROM that can be used from the BalCheckHR in case the original ROM has problems.

Bank 2 - Z80 Check - A program that checks the Z80 without using screen RAM.

I don't have either the "Remote ROM" or the "Z80 Check" software.

Thank you, Matte, for your dedication to this project!

Adam

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Michael updated me again on April 21, 2019.

Here are Michael's comments:

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Did some experimenting with my hi-res static RAM scheme on my quick-connect breadboard. The single static RAM chip is now running perfectly in low-res and hi-res using my variation of the Datamax UV-1R RAS and CAS timing scheme. This timing scheme puts out one RAS line and four CAS0, CAS1, CAS2 and CAS3 lines, essential for operating 4 static RAM chips in hi-res. The RAS line latches in the row address from the custom address chip using a 74F373 for the static RAM chip A0-A5 pins. Each CAS line is used as the static RAM's chip select. The column address from the custom address chip will appear at the static RAM A6-A11 address pins. Three Datamax drawings are archived on the Bally Alley in my hi-res Package 3 doc located within the website's Documentation section. Besides the hi-res write only routine for the first hi-res chip, I also wrote a write/read RAM test routine similar to the commercial Balcheck low-res RAM test. Both of these 2 hi-res routines are running perfectly on this single static RAM chip. The other 3 required hi-res static RAM chips are "simulated", described in a previous email, and display constant vertical TV graphics (colors) defined by grounding or floating specific 74LS166 input pins. I am going to use my logic analyzer to take a closer look at the RAS and CAS timing during a write and a read attempt and maybe do some more experimenting with the scheme on my breadboard. After that, I will try to get 2 static RAM chips running perfectly in hi-res. I am expecting to have to debug this next step because it will utilize two 74LS245 chips, which may pose problems I won't describe here.

Allen called me yesterday. He's using BalcheckHR on a failed motherboard powering on with a blank TV screen. I would have loved to see the look on his face when he ran SetScreen3 for the first time and saw it display TV graphics. He's already saved himself time and frustration by running Balcheck and Setscreen3.

I am putting aside my hi-res static RAM project for a while. I'm going to work on the 2 Wav files for my BalcheckHR slightly revised, remote 8K on-board ROM and the Z80 Check routine. After that, I will attempt to record an hour long DVD running my hi-res MLM and BalcheckHR including the hi-res routines. This DVD will not go in-depth, but will simply be an introduction to the 2 software packages. The hi-res Pixel Stringer will be the last recording. I plan to introduce it verbally and then just let it run to fill up the hour long (or longer?) DVD.

Finally, I will be spending less time daily on my Astrocade projects so I can work on a big pile of chores and pursue additional interests. [...]

Bye.

MCM

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There's a lot about this update that I like, but probably the best news is to see that a BalCheckHR unit has gotten into the hands of someone who can use it.

Adam

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Michael updated me again on April 23, 2019.

Here are Michael's comments:

----------------------------------------

I implemented my "tweeked wiring change'', used on my quick-connect breadboard, to my previously wired static RAM wire wrap board. I have good news and bad news to report.

I ran on the WW board, a single static RAM chip in both the low-res and hi-res modes, observing what was and was not working. I added the 2nd static RAM chip and 74LS245 chip, ran the board in the hi-res mode only and observed the run. Based on what I was observing, I decided to add the remaining two static RAM chips and last two 74LS245 chips to see what would happen.

The good news is that I was able to adjust the RAS line trimmer pot, so my hi-res SetScreen, write only, "Fill Screen" routine would execute perfectly. This is the first time I have seen my "modified for hi-res" Astrocade motherboard run perfectly in hi-res using only 4 static RAM chips.

However, my write/read, first chip only, RAM test routine would not execute. It looks like the Z80 CPU can write to all 4 hi-res static RAM chips, but is having difficulty reading bytes from the hi-res screen RAM. I have seen this difficulty before using just one static RAM chip.

My "Fill Screen" routine is a simple plop write to screen RAM. The next step will be to run some magic writes on the hi-res screen to confirm my present wiring scheme on my WW board is indeed working perfectly in the "write only" mode. I will program a "write only" version using a portion of my original hi-res demo. If I can write magic static graphics with no problems, then I will try to move a hi-res critter around the screen using XOR write/blanks. I will not be able to use Z80 Call/Ret instructions, which require a readable stack area in screen RAM. Instead, I will use JP(IX), JP(IY) or JP(HL) instructions as a substitute for a Ret instruction. I am taking this particular next step, because there's a pretty good chance this new, write only, magic graphics test routine will work perfectly. If so, this progress will keep me highly motivated to continue my work on this project, which lately has been a struggle and time consuming. Another issue has been related to the use of my logic analyzer, which at times, has been puzzling me, because I am seeing portions of waveforms that don't seem to be displaying as expected. So, I am questioning the accuracy of my LA.

It looks like I'm going to spend time using my LA on the static user RAM in my hi-res Astrocade, to see if I can determine approximately how much time it takes the output data to appear at the chip's data pins when the Chip Select line goes low, during a Z80 read request. Then, use that observation and compare it with my WW board's read issue. Hopefully, I'll be able to resolve this hi-res screen RAM read issue.

I've spent a lot of time on this project and will continue to work on it until I run out of ideas to debug the wiring scheme. But, I will now work on this project at a much slower pace, so I can pursue other interests.

Bye.

MCM

----------------------------------------

Michael is making some good progress here, and I'm glad he shares these in-progress reports.

Adam

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Michael updated me again on April 29, 2019.

 

Here are Michael's comments:

 

----------------------------------------

 

In my last report, I indicated I ran my hi-res "Screen Fill" graphics routine on my hi-res static RAM wire wrap board with all 4 static RAM chips installed. I was surprised to see the routine execute perfectly. I also indicated, I wanted to test the present wiring scheme on the wire wrap board using magic graphic writes. Because I was so excited about this latest successful attempt, I decided to create a magic "write only" program right away. I didn't want to wait 2 or more weeks to see if the present wiring scheme could handle magic writes perfectly.

 

The last several days, I made a big push to create a 1100+ bytes "write only" program similar to my 1980's original hi-res demo. I was able to write the fish tank plus 14 static graphic patterns with magic function variations. Since this program was a "write only" test, I could not utilize a screen RAM stack area, save data in screen RAM or execute call/ret instructions. This limited me to only 6 alternate Z80 CPU registers plus the Z80 I register to save variables. Because of this limitation, I could not include moving a critter around the screen using magic XOR write/blanks.

 

After creating, debugging and running the magic test program on my hi-res Astrocade, I ran the program on my hi-res static RAM wire wrap board. I'm excited to report it executed perfectly. Attached to this report is a screen shot of the test. The shot is a bit crude being a RF modulated TV display, but it proves my claim of successfully writing magic graphics on a 4 static RAM chips configuration. Also attached are some photos of this project's circuit board set up, including the "modified for hi-res" motherboard, static RAM wire wrap board and the quick-connect breadboard. The motherboard used is MCM Design's 2nd "modified for hi-res" board. This 2nd board has all 28 clocks/data lines, necessary for operation in the hi-res mode, wired to a 28 pin wire wrap socket mounted on the bottom of the motherboard. The motherboard's 50 pin expansion is not required for this wiring scheme. The keypad was removed long ago to be utilized as a remote keypad for MCM Design's hi-res Astocade.

 

[There are the seven photos that Michael provided. Descriptions of each are throughout this post.]

 

Hi-Res Test Cartridge:

 

post-4925-0-82887300-1556816163_thumb.jpg

 

Magic Writes Test:

 

post-4925-0-97054200-1556816164_thumb.jpg

 

Modified Motherboard

 

post-4925-0-10901000-1556816166_thumb.jpg

 

Power On Test:

 

post-4925-0-33908900-1556816167_thumb.jpg

 

Quick-Connect Breadboard:

 

post-4925-0-55109700-1556816168_thumb.jpg

 

SRAM Project Set Up:

 

post-4925-0-72209300-1556816169_thumb.jpg

 

Wire Wrap Board:

 

post-4925-0-94878500-1556816170_thumb.jpg

 

The wire wrap board is sized to fit inside the hi-res Astrocade as an optional replacement board. This wire wrap board has room for the optional multi-page screen RAM interfacing plus user RAM. The wire wrap board is powered by a single +5V supply. The board also has provisions for 5V, 12V and -5V connections to a future composite video and audio driver board that will replace the Aztec RF modulator.

 

The set up photos are preliminary since this project is still in its development phase. Whether or not there will be a 2nd final wirewrap board for use with a custom console will be dependent on the success of this project. This 2nd hi-res console by MCM Design may be strictly a hi-res game player.

 

There is also a screen shot of the hi-res static RAM wire wrap board powering on with a minimal screen set up and Z80 CPU halt instruction. This shot shows all 4 static RAM chips powering on normally (perfectly). The test routine does not clear or write any data to the hi-res RAM, so what you see is the graphics (data) in RAM immediately at power on. This minimal hi-res power on routine was used initially to test the 1st static RAM chip in hi-res.

 

The next issue for this project is to get the Z80 CPU to read all screen RAM perfectly, which apparently requires more precise timing. This issue will probably be the most challenging of this project to resolve. I am hoping to debug this problem. Should I successfully tweek the timing so the Z80 can read screen RAM, then all that would be left on this project to implement would be the 8 hi-res multi-page screen RAM interfacing.

 

OK, now I am ready to put this project aside for 2 or 3 weeks, take a break from the project's frustrating challenges and work on something easy. I will now work on the 2 ROM BalcheckHR files not released yet and also my 1 hour DVD introducing BalcheckHR and hi-res MLM.

 

Bye.
MCM

 

----------------------------------------

 

It's great to see these pictures along with the reported progress.

 

Adam

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I added two additional cartridges images for the BalCheckHR hardware by MCM Design (Michael Matte).

This hardware allows experienced electronics users to diagnose many problems with a Bally Arcade/Astrocade game console. The new 8K ROM images included in the archive are the following:

1) BalcheckHR RemoteROM - A slightly revised 8K on-board ROM that can be run from the BalCheckHR hardware.

2) BalcheckHR Z80check - The intent of the "Z80 Check" program is to visually confirm the Z80 CPU is operating by watching the dual display to see if it counts up from 00 to FF in hexadecimal.

http://www.ballyalley.com/emulation/cart_images/cart_images.html#BalCheckHRAstrocadeROMImage

The Z80 sourcecode for "Z80 Check" is also in the archive. It can be assembler with the ZMac Z80 assembler.

Enjoy!

Adam

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Michael updated me again on August 26, 2019 about his Hi-Res Static RAM Project.

 

Here are Michael's comments:

 

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The last several days I have been working again on my hi-res static RAM project. I am very excited about this update and have seen major progress on the project last Saturday. I won't mention the changes I made to my wire wrapped hi-res static RAM project board.

 

First, the board runs perfectly in low-res. The board is strictly wired for hi-res operation. If I do build a second hi-res Astrocade, it will run  strictly in hi-res. To run the project board in low-res, one chip must be removed from its WW socket, then one socket pin must be wired to the socket's ground pin using a small jumper wire. I tested the board in low-res with a bunch of games and demos. My 10 Fish Demo is a good test for run perfection because it moves around 10 fish using the magic XOR write and blank. I ran that demo for 1 hour. Perfect!

 

MCM Design has now proven, using 2 different hardware schemes, that a modified Bally motherboard can run perfectly using one static RAM chip. A minimal setup requires one static RAM chip, one 74F373 chip (or two 74LS75 chips) and one 74LS32 gate. A 74LS373 chip will likely work. Eighteen timing lines are required, which are all available where the standard Bally motherboard 8 dynamic RAM chips are located. There may be enough room in this motherboard area to place the required 3 chip PC board for such a modification.Yes, I know that is a lot of wiring to work with. So, as long as replacement dynamic RAM chips are available, a static RAM chip modification would be a last resort. One last note. The insulation on #30 wrapping wire stands up easily to a 20W soldering iron. Wrapping wire was used on MCM Design's hi-res Astrocade as tap wiring soldered to the Astrocade motherboard.

 

I have also made progress with the project board in the hi-res mode. In my last report, I indicated the Z80 CPU was writing great to hi-res screen RAM, but was having difficulty reading from the hi-res screen RAM. Now, the project board is executing nearly perfectly all of my hi-res demos and programs which I attempted to run. I changed a few bytes in my BalcheckHR 8KB EEPROM, so the entire chip can run in the hi-res mode. All of these demos and programs executed. This is the first time I saw my new hi-res "Pixel Stringer" demo execute on this project board. That is a really cool demo.

 

However, even though the project board is executing hi-res demos nearly perfectly, now the video display is producing a lot of narrow, short horizontal glitches. These gliches are a part of the custom data chip's TV display scan from hi-res RAM. The project board is also having some trouble moving hi-res patterns around the screen using magic XOR writes and blanks. I have seen this particular difficulty before during this project. The problem is a visual indication that the timing is a little off somewhere on the board. I think the problem is with the active-low CAS line, which is used as the static RAM chip select (CE). So, I'm going to focus, for now, on that timing signal using a logic analyzer and try to clean the signal line up, because I know it isn't quite acting as it should.

 

 I was really surprised and excited last Saturday when I saw the project board executing hi-res demos nearly perfectly. This new progress has indeed refreshed my motivation to continue working on this project.

 

Bye.
MCM

 

----------------------------------------

 

Michael is still making good progress, and he is inspiring himself-- that's fantastic!

 

Adam

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Michael updated me again on August 30, 2019 about his Hi-Res Static RAM Project.

 

Here are Michael's comments:

 

----------------------------------------

 

Adam, I had to send you this quick note. I think I resolved the magic XOR graphic write and blank issue. I replaced the RAM chips with faster chips, 85ns access as opposed to 120ns access. As I speak, I'm running the low-res 10 Fish Demo on the hi-res screen map. This demo was producing the most pixel glitches. Now, it's been running for over 40 minutes and there is not one pixel glitch. I'll run some more demo tests.  Looks like the project board is executing hi-res graphic programming perfectly. The TV display scan glitches are still there though. The CAS0 thru CAS3 lines may be running a little dirty, I'm guessing. I'm forced now to use a "hit or miss" approach to resolve this last issue. I'm going to try first a series resistor, then a pull-up resistor in these 4 CAS lines to see if that will eliminate those display scan glitches. Man, I'm so close to perfecting this project. Just one last issue to fix. I'm really excited about this achievement today. I can't tell you how many hours I have put into this project. Will I reap the fruit of perfection in this project? Time will tell.

 

Bye.
MCM

 

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Michael updated me again on September 11, 2019.

 

Here are Michael's comments and pictures:

 

(These can also be seen on BallyAlley.com, here:)

 

https://ballyalley.com/documentation/hi-res_packages/hi-res_packages.html#HighResolutionStaticRamUpgradeMCMDesign

 

----------------------------------------

 

A MCM Design Announcement

 

MCM Design is pleased to announce a breakthrough in the high resolution RAM configuration for the 1970s Bally Arcade 3 custom chip set. Up to now, four 4KB banks of dynamic RAM were required to operate the 2 Bally custom address and data chips in the high resolution mode. Since each bank utilizes 8 DRAM chips, a total of 32 DRAM chips was necessary. However, MCM Design has developed, built and tested a prototype wire wrapped RAM board which can operate the same 2 custom chips in high resolution using only 4 static RAM chips. MCM Design's breakthrough static RAM configuration also offers single +5VDC power supply operation with optional user programmable multipage screen RAM capability.

 

Below is a listing showing the major chip differences between MCM Design's new hi-res static RAM scheme and the coin op arcade Seawolf II.

 

                                                                MCM Design                                      Seawolf II

                                                                scheme                                                scheme

 

RAM                                                      4 static RAM chips                            32 DRAM chips

                                                                4KB x 8 bit                                           4KB x 1 bit

                                                                4KB capacity minimum                   4KB capacity minimum

                                                                120 nsec access time

                                                                (or faster)

 

video data bus                                  four 74LS245                                      one 74LS245 (optional)

                                                                bidirectional receiver                     four 74LS253 (read only)

 

data bus enable                                74LS138

                                                                enable selector

                                                                74LS132

                                                                selector decoder

 

active-low RAS clock                       74LS123

                                                                2 inverter gates

 

row address latch in                        74LS373

 

active-low                                           74LS175

CAS0, CAS1, CAS2, CAS3

generation

                                                                _______                                             ______

 

Total chips                                                13                                                          37

 

 

 The total chip count for MCM's new scheme is 25 chips. A few more chips must be added to:

 

1. Run the screen RAM in low or hi-res modes.

2. Multipage the screen RAM.

 

 

HOW THE NEW SCHEME WORKS

 

The new RAM timing scheme is a variation of the scheme used by the DATAMAX UV-1R computer. Three DATAMAX UV-1R schematics are archived on the Bally Alley website in the Documentation/ High-Res Astrocade Upgrade/ High-Res Package 3 section.

 

Memory Address Selection

 

The active-low row address strobe RAS is generated from the negated system clock ɸ (phi) using a 74LS123 chip and 2 inverter gates. The memory row address, from the custom address chip lines MA0-MA5, appears first and is fed to a 74LS373 latch. This row address is latched at the static RAM chip A0-A5 input pins by the active-low RAS line.

 

The memory column address on the same MA0-MA5 lines appears next and is also wired to the static RAM chip A6-A10 input pins.

 

Both the row and column addresses now present at the static RAM address pins are then latched into the static RAM chip by the active-low CAS line which acts as the RAM chip's enable (select) line.

 

Bank Select

 

The four custom address chip lines RAS0, RAS1, RAS2 and RAS3, which are used as the RAM bank select, are fed thru two 74LS175 quad D-type flip-flops to generate the four static RAM chip  active-low enable lines CAS0, CAS1, CAS2 and CAS3.

 

The 8 Bit Data Bus

 

A static RAM chip shares its 8 bit data in/out lines. The two DATEN and active-low Write Enable (WE) lines determine if data on the 8 bit data bus MD0-MD7 is to be written (input) into the RAM chip or read (output) from the RAM chip.

 

The  8 bit data bus from each RAM chip is wired to one of four specific 74LS245 bidirectional receivers. The line side of each of these 4 chips are all wired to the custom data chip MD0-MD7 pins. The custom data chip DATEN line is wired to the Direction (DIR) pin of each 74LS245 to direct the data flow as a write or read. A decoded enable line is also wired to each 74LS245 enable input so that only the appropriate 74LS245 will be enabled (turned on) at the right time to avoid any data conflicts.

 

Screen Refresh (Scan)

 

When all 4 RAS0, RAS1, RAS2 and RAS3 lines are simultaneously active-high, a TV display refresh (scan) is generated. All four 74LS245 receivers are disabled at this time. This scan acts like a memory read. One byte from all 4 RAM banks is read simultaneously. So, these 4 bytes (32 bits) of data are fed to the four 74LS166  chip shift data inputs. An active-low Shift Load (S/L) input to the four chips indicates when the data is valid and ready to be shifted serially, two bits at a time by the 7M clock, into the custom data chip using the two Serial 0 and Serial 1 lines. Apparently, there is a 12 bit address counter in the custom data chip which keeps track of the row and column addresses, so the entire screen RAM is scanned. So, 4 bytes (16 pixels) at a time are shifted into the custom data chip every time the S/L line goes low.

 

 

MCM DESIGN's  INTENT WITH THIS NEW HI-RES SCHEME

 

This new static RAM scheme was developed for personal use with the Bally/Astrocade home computer system to supersede MCM Design's original hi-res Astrocade and to utilize this second modified Astrocade as a purely hi-res gamer. In order to implement the new static RAM scheme, modifications MUST be made to the Astrocade's motherboard. The primary modifications are listed below.

 

1. Remove the 8 DRAM chips and also chip U23.

2. Remove from ground, the Serial 0 and Serial 1 input lines at the custom data chip.

3. Move the 27 ohm, 1W power resistor R1 over about 1 inch, so a 28 pin ribbon cable WW socket can be     mounted on the motherboard.

4. Tap 28 specific motherboard lines to the WW socket using #30 wrapping wire, one end soldered to the motherboard, the other end wrapped to the WW socket.

 

No connection to the Astrocade motherboard 50 pin expansion is necessary to operate this new hi-res static RAM scheme.

 

MCM Design is announcing this new scheme and plans to post detailed scheme documentation on the Bally Alley website for a high tech minded individual desiring to take the challenge and build a "modified for hi-res Astrocade" which can run in the low or high resolution modes. MCM Design also plans to convert certain low-res Astrocade games into hi-res. Note that over 8KB conversions will need to run on 32KB user RAM addressed 8000-FFFFH. Some hi-res demos are already included in the 8KB BalcheckHR package already archived on the Bally Alley website.

 

MCM Design is extremely pleased with the results of this new hi-res static RAM prototype board. It runs perfect in low and hi-res and has a low chip count. It is awesome! MCM Design will now develop  and test the option for multi-paging the screen RAM.

 

I would like to thank Ken Lill for his recommendation to me in purchasing the 16 channel Kingst logic analyzer, which resolved several project problems. I would also like to thank Anthony Miller for his detailed "A Description Of The Bally Professional Arcade Video Hardware And Associated Coin-Operated Hardware" and the Bally Alley for posting the documentation. This doc detailed the hi-res screen refresh (scan) function and circuitry, which was a major help in understanding and resolving this project's final problem. Without this outside help, I would have never successfully completed my hi-res static RAM project scheme. Thanks for your help.

 

 

MCM Design

Sept 2018

 

 

HR Static RAM1.jpg

HR Static RAM2.jpg

HR Static RAM3.jpg

HR Static RAM4.jpg

Edited by ballyalley

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