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Processor speed measured: 0.136 MIPS


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I am pretty sure the result is not much news to any experienced TI-99/4A assembly programmer, but I became interested in understanding how fast the TMS9900 runs while running some "standard" software. So built a device to do the measurement, and the result is that the speed while running Parsec is around 0.136 MIPS. I created a very short youtube clip about it too.

 

https://youtu.be/XgwzXQh7tLU

 

This mini project was more about getting better up to speed with the NXP LPC43 series microcontrollers I've been wanting to interface with the console. I figured this must about the simplest circuit one can build that still provides an interesting piece of information (I only had a limited number of time to spend and I wanted to get that all important sense of achievement). I was also curious to understand what is the processor speed of my FPGA TMS9900 CPU, so I figured a nice starting point is to measure the original console first before looking at the FPGA system.

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The processor is nice and patient with us. That is why I love it. Whenever I think something I'm interfacing to the TI is maybe too slow, I have so far, always been able to check the facts, and just rule it out (short of gross error).

 

The video is 'unavailable' according to youtube, but who knows, I might just be in the wrong country...

 

-M@

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The processor is nice and patient with us. That is why I love it. Whenever I think something I'm interfacing to the TI is maybe too slow, I have so far, always been able to check the facts, and just rule it out (short of gross error).

 

The video is 'unavailable' according to youtube, but who knows, I might just be in the wrong country...

 

-M@

 

 

Thanks for the comment, I had messed up the settings in YouTube, hopefully the video now shows up. It is only about 20 seconds.

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136,000 instructions per second. :(

 

So sad and yet we love our 9900 just the same.

 

So your new machine full tilt should come in at over 4MIPS based on some of your other posts.

That's a nice number.

 

136,000 instructions per second isn't just a good idea, it's the law! Er, of TI-99 retro-coders, anyway.

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That table makes sense. Even if the MIPS number for the TMS9900 is low, we need to remember that when comparing to the 6502 or Z80 the TMS9900 is handing everything in 16-bit. Doing comparable operations on the 6502 would be much slower. The Z80 can do (some) 16-bit math, but one quickly runs of of register with that. Also the addressing modes of the TMS9900 are very neat and powerful - one of those "slow" TMS9900 instructions can do heck a lot of stuff.

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Even if the MIPS number for the TMS9900 is low, we need to remember that when comparing to the 6502 or Z80 the TMS9900 is handing everything in 16-bit. Doing comparable operations on the 6502 would be much slower.

 

:)

 

You could easily begin to argue for the opposite. 8-bit instructions use less memory than 16-bit instructions. Why do 16-bit operations when you can do a job in 8-bit? Why do read before a write when you're moving 16-bits? Why all the 8-bit instructions? Etc.

 

Within the TI-99/4A environment, we end up doing a lot of 8 bit stuff anyway, and at least relatively to the 9918A. Instruction counts on running programs have the MOVB byte instruction coming out on top.

 

http://atariage.com/forums/topic/212292-/page-2?do=findComment&comment=2754544

 

Looking at the instructions in use, one can't help thinking about at least one effective Z80 instruction, namely the DJNZ, Decrease and Jump if Not Zero.

 

;)

Edited by sometimes99er
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:)

 

You could easily begin to argue for the opposite. 8-bit instructions use less memory than 16-bit instructions. Why do 16-bit operations when you can do a job in 8-bit? Why do read before a write when you're moving 16-bits? Why all the 8-bit instructions? Etc.

 

Within the TI-99/4A environment, we end up doing a lot of 8 bit stuff anyway, and at least relatively to the 9918A. Instruction counts on running programs have the MOVB byte instruction coming out on top.

 

http://atariage.com/forums/topic/212292-/page-2?do=findComment&comment=2754544

 

Looking at the instructions in use, one can't help thinking about at least one effective Z80 instruction, namely the DJNZ, Decrease and Jump if Not Zero.

 

;)

 

 

Yes, no argument here :)

I actually first learned assembly programming on the ZX Spectrum and spent a lot of time back in the day calculating the T states.

 

Regarding your point the TMS9918 access - I am really tempted to add into my FPGA TI-99/4A just a direct 16-bit path to the video memory, just mapping the VDP memory into the memory map of the TMS9900. It would be trivial to do with the FPGA. No legacy software would be able to use it, but it could be fun to create customised versions of some existing games to see what could be done with faster CPU and video memory access.

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I am pretty sure the result is not much news to any experienced TI-99/4A assembly programmer, but I became interested in understanding how fast the TMS9900 runs while running some "standard" software. So built a device to do the measurement, and the result is that the speed while running Parsec is around 0.136 MIPS.

 

That's cool. :thumbsup:

 

Could you try out a few other cartridges, games and what not, perhaps even a game running in TI Basic. I expect the MIPS to be around the same or less. Games with code in ScratchPad like Parsec should perhaps give an overall +0.01 MIPS.

 

:)

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Yes, no argument here :)

I actually first learned assembly programming on the ZX Spectrum and spent a lot of time back in the day calculating the T states.

 

Regarding your point the TMS9918 access - I am really tempted to add into my FPGA TI-99/4A just a direct 16-bit path to the video memory, just mapping the VDP memory into the memory map of the TMS9900. It would be trivial to do with the FPGA. No legacy software would be able to use it, but it could be fun to create customised versions of some existing games to see what could be done with faster CPU and video memory access.

 

 

Is there any space in the world for an intellectual property like yours for the CPU with VIDEO processor, some other I/O, some on chip very fast RAM for registers sets and perhaps a small RTOS ? Selling it as a realtime platform?

 

I ask because the simple 9900 has very repeatable timing and many processors now do not.

And using the RTWP based context switcher that I played with creates a very fast task switcher.

 

Or has ARM sucked up all that air in that space?

 

(been out the electronics field as a job for 16 years) :-)

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Keep in mind that some of the benchmarks I've seen out there for the 6502 are highly tuned.
I saw one where a simple benchmark that should have been under 256 bytes was 16K or something crazy like that because he had created so many tables and unrolled the loop so many times.
He also wrote the 6809 version of the benchmark and proceeded to use one of the index registers that requires some of it's operations to use 2 byte opcodes instead of 1.
I tried to get him to swap index registers but it was pretty obvious he had no intention of doing anything to make the 6809 code better.

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  • 1 year later...
On 11/6/2017 at 8:02 PM, JamesD said:

Keep in mind that some of the benchmarks I've seen out there for the 6502 are highly tuned.
I saw one where a simple benchmark that should have been under 256 bytes was 16K or something crazy like that because he had created so many tables and unrolled the loop so many times.
He also wrote the 6809 version of the benchmark and proceeded to use one of the index registers that requires some of it's operations to use 2 byte opcodes instead of 1.
I tried to get him to swap index registers but it was pretty obvious he had no intention of doing anything to make the 6809 code better.

MIPS is somewhat a inaccurate way to measure processor speed.

For example the z80 can perform instructions that goes from only 4 T-States to 23! So what is MIPS? 

the 6502 range from 2 Clock Cycles to even 7!

Plus they are heavily influenced by the clock frequency.

 

Performance of a CPU cannot be measured barely by counting how many instructions can be processed per second.

So TI's CPU can show a small MIPS value, but i do not think it is so slow as MIPS comparison say.

 

Plus, even the clock speed is not a valuable way. Take for example the C64. It has a 6502 @ 1Mhz. Slow compared to Z80 @3Mhz. So one can think: "Why not increase 1Mhz to 3?" The 6502 with only 7 cycles in the worst case will outperform thhe z80!

 

This is possible teoretically:

But even 1 2Mhz 6502 could not be done on C64 because of the tightly coupling between VIC-II (that share memory with CPU) and CPU.

When Commodore released the C128 they pushed the speed to 2Mhz but have to DISABLE the VIC-II and use another "VDP" similar to the TMS in the way it worked (no shared mem)

 

 

 

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  • 2 months later...

For the TMS 9900, 70% of the instructions require 14 clock cycles or less. Minimum is 8 cycles. If we settle for an average of 12, then that implies 0.25 MIPS for the TMS 9900. Now of course not adding any wait states, extra memory accesses for addresses etc.

Thus it will not get any faster than this.

Multi-bit CRU instructions, shifts and advanced math takes significantly longer time to ececute. On the other hand, 52 clock cycles for MPY, compared to the complex sequence of instructions required for a CPU like the 6502 or Z80, is still fast. A reasonable 16-bit multiplication algorithm (32 bit result), using shift and add, for the 6502 would require around ten times the number of clock cycles as the MPY instruction requires. If the frqcuency then is 1 MHz for the 6502, vs. 3 MHz for the TMS 9900, we're looking at 30 times longer to do such a multiplication.

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