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okay, I ended up having to refund my money for the sram, since it never arrived, but I was able to instead buy 128k worth of sram in a lot of 4 separate 32K chips for the same price, im using two of them one for normal program/data ram to extend from the 128bytes, which the atmega8515 will act as a mmu to read from and write to ram using the upper address bits to access either the mmu or the the dual port ram (IDT7130SA55) which would act as a memory buffer, though i am considering using atmega644 instead of an 8515 for its extra memory, only difference is no port E and but much more memory versus the 8515, but the 6502 would write to the ram, which the atmega would either do nothing, store it, or load it and do some processing, and store back to the dual port ram or store in in its own 32k for later use or vice versa. also i would use the atmega to control the tia and 6502, using the 6502 itself, i.e having the 6502 trigger the atmega which would halt the 6502 using its rdy line, and assume control of the tia, thing is either you can use the 6502 for addressing the tia, but would be limited to the 1.19 mhz clock (both atmega chips will run @ 21.47727MHZ) , or instead use atmega to handle the tia bus, but the way i would implement this i think most likely would break normal 2600 compatibility unfortunately.

 

TL;DR

 

i had reorder sram but got a better deal , i've gotten some dual port ram, current progress is getting the memory map structured properly so that if you plug in a 2600 cart it will run just fine, but you insert a cartridge with homebrew code that would read and write to the extra address space, then you can use the extra hardware added to the system and use the 32k of ram and the dual port ram which the display co-processor would sit behind with its own 32k of video or just general purpose ram (ie you could store graphics or program data or both if you wanted to).

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Well I got a 2600 Jr mobo, I've boiled it down to having the 6502 communicate with an atmega644 driving 32k of sram and an ay-3-8910 which also has it's own 16bit gpio for additional expansion, with a few signals taken from other places you could make a small expansion port (well that's the idea) the 644 will hold a small kernel that consists of sound player rountine/gpio handler and accelerated TIA ("ATIA" mode, the 6502 can write the frame to the 644 which can store it in ram, then simply have the 6502 update the parts of the frame that have changed, and whatever hasn't will be free cycles for the 6502 minus keeping sync.

 

PS: I HAVE A DAY JOB SO I DONT GET PUT MUCH SPARE TIME TO WORK ON THIS, BUT THERE IS PROGRESS..

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Okay I finished socketing this junior mobo, replaced the tia as the co10444d seems to have a better video output vs the um6526, replaced the 6532 aswell, I'm waiting on pin headers for the cpu socket, with the 6502, atmega644, ram and ay-3-8910 connected on a plugin board, (I didn't have a 28pin socket so I just cut a spare 40pin one down)post-30967-0-90750700-1529800016_thumb.jpg

 

 

post-30967-0-82330600-1529800171_thumb.jpg

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Okay I have a prototype daughter board in progress, essentially the atmega will handle the ay-3-8910 (32k of ram would be addressed through it's "gpio" with the ram data bus connected straight to the 6502) the pic and 138 are for generating outputs for chip selection (bankswitch), essentially the extra hardware would be outside the normal 6507 memory map, so that any stock 2600 cart could run, but would just allow one to write code for a normal 6502, but also by using the upper address space to use the atmega to do tasks while the CPU is drawing the screen, as well as taking control of the bus, the atmega would have a bootloader that would sit idle until it was addressed directly from the 6502. It simply controls the banks (which the pic and 138 are there for, disabling the Tia, riot,ram,etc)

As well to allow it to play music from the ay38910(combined with the Tia audio, five independent sound channels!) and to halt the CPU and control the Tia if needed

 

post-30967-0-74320400-1530986089_thumb.jpg

 

post-30967-0-00146800-1530986108_thumb.jpg

Edited by universal2600

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Finally got the rest of the components (minus a spare 6507), so the board sits snug ontop of a pin header connected directly to the 6507 lines, which would connect to the 6502(no not the one in the picture I have a new one I haven't opened it yet),I plan to use the pic, 138 and gal20v8b (lattice, yes it's obsolete, but it allows one to change the memory map just by flashing a chip😁........and its 5v), as glue logic so I can halt the 6502, generate chip selects, set up in the end you would write to locations that's normally outside the 6507 map, that could represent an instruction to the atmega to set the ram address (using the ay38910 ports) to read or write, and to allow the atmega to drive the tia while halting the cpu,or use the atmega to play sound through the ay38910 (ym player?)

post-30967-0-44083700-1531784306_thumb.jpg

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this project is not dead, so i've been making a custom pcb, using the 6502, tia, 6532, atmega8515 (this will be running at 21.477 mhz), and cxk58256 sram (32k), essentially the 6502 will act normally until you start to write to the upper bits a13-15, which connect to the atmega, and you would be able to store/load a byte (from or to the 6502) from the 8515 which would be programmed to be able to copy data from the the bus to external ram, or copy it to internal memory and do operations on such data; for example, be able to pre-process data, for better sound capabilities (generating sounds in software using the 8515, with little or no cost on 6502 performance), one can implement a frame-buffer using the 32k and 8515 to pre process the display in 32k ram and just store the location of this data in the riot to have the 6502 draw or just halt the 6502 (might put tri-state logic on the 6502 signals so the 8515 can just dma to the tia)

 

pretty much have like 90% of the bus signals connected, i have to rearrange some aspects, everything minus control signals clock and analog outputs (tia) are connected (pretty much power clock r/w, oe, polarity/control/video/sound signals)

 

essentially you can write an 8bit value to the 8515, using 3 address lines, the 8515 would be programmed to use 3 bits on port E as instruction registers, (256 x 3 different instructions, you wouldn't need 768 total instructions, but this would allow one to make special instructions for their specific purpose simply by changing how the 8515 rom decodes it, by toggling port E and then providing an 8bit value which the 8515 would decode into an operation which then you would write the data to the 8515 which operation/function specified before would preform on, then store it internally, to 32k ram, or spit it back to the 6502 bus

 

post-30967-0-71414700-1545609311_thumb.png

 

post-30967-0-71568500-1545609315_thumb.png

 

post-30967-0-24513900-1545609320_thumb.png

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Posted (edited)

Cool project. Still following. Any updates?

yeah slowly but i still work on it from time to time, I've been having real life getting in the way (work, medical bills due to dislocated shoulder, priorities..... )

 

the hard part is mapping the memory that would allow for full compatibility up to vcs 8k at least, mainly to have the 2600 mode on power on, so if there is vcs code loaded it'll just boot like a normal console and play as a normal console, and simply by jumping to addresses out of the 6507 bus ( a13 - a15), you simply would then go about initializing the extra ram, sound, and coprocessor, the ay8910 port is used to address 32k of ram, another 32k connected to the cpu, plus 128 bytes on riot, which could be used in the enhanced mode as cache or used as stack space, im stuck between the atmega 8515 and 644 (8515 is designed perfectly for this purpose the 644 literally is the same with more memory but port E removed..why..

[which would make bank-switching/chip selects easier])

 

atm my board has the tia, 6502, riot, 8910, 644 and a gal20v88, with 64k total ram (sram) ( gal would be used for chip selects and bank switching) it's really now either make up my own memory map and then i could just make it as any other home brew computer, it would not be code compatible with 2600 software, however the software could still be ported...just have to modify code to use the new memory map, or keep as much 2600 compatibility which may limit the expansion hardware, as well i still have to write software for the atmega to handle dma for the tia chip, which either has to sit on its own bus or tristate the 6502 (extra logic needed for this) , since the tia operates solely as a slave (it only receives data sent to it, doesn't "transmit" any info, you have to stream data to it to have it do anything). plus all code would have to be done in assembler (not hard just takes more time) plus 6502 code to be able to use the extra hardware

 

i was contemplating using a cpld (emp240t dev board) to provide to glue logic to mitigate these issues, and would allow me to be much more flexible...but it's 3.3v and needs level shifters (low parts count makes pcbs cheaper to make) , but it has an onboard 50mhz which would help reduce some parts ( i could derive the atmega, tia, and cpu clocks from this by dividing it internally in the cpld, which also could be used for mmu functions or as a sort of buffer between tia and 6502 (which the atmega could use to access the tia and the cpld will simply override/tristate the 6502 bus and let the 644 write to the tia )

 

one question if your code starts at $f000 how does the hardware at power up know to jump there?, iirc it stars from $0000 which is accessing tia or riot then cartridge (this is why you shouldn't use CPU address lines as chip selects)

 

plus if there is enough interest i could make a few boards for anyone interested in it (hardware side is easy, but coding assembly will take a bit of time for me) to play with and develop software for it, just pm me

 

 

post-30967-0-38627100-1551806164_thumb.jpg

 

post-30967-0-43111600-1551806282_thumb.jpg

Edited by universal2600

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yeah slowly but i still work on it from time to time, I've been having real life getting in the way (work, medical bills due to dislocated shoulder, priorities..... )

 

the hard part is mapping the memory that would allow for full compatibility up to vcs 8k at least, mainly to have the 2600 mode on power on, so if there is vcs code loaded it'll just boot like a normal console and play as a normal console, and simply by jumping to addresses out of the 6507 bus ( a13 - a15), you simply would then go about initializing the extra ram, sound, and coprocessor, the ay8910 port is used to address 32k of ram, another 32k connected to the cpu, plus 128 bytes on riot, which could be used in the enhanced mode as cache or used as stack space, im stuck between the atmega 8515 and 644 (8515 is designed perfectly for this purpose the 644 literally is the same with more memory but port E removed..why..

[which would make bank-switching/chip selects easier])

 

........

 

one question if your code starts at $f000 how does the hardware at power up know to jump there?, iirc it stars from $0000 which is accessing tia or riot then cartridge (this is why you shouldn't use CPU address lines as chip selects)

 

If you're trying to be completely VCS compatible, you'll want to avoid utilizing A13-A15 as triggers for your "enhanced mode". Atari 2600 bankswitched games usually utilize different addresses in different banks. i.e. Congo Bongo uses $Fxxx in the first 4k bank and $Dxxx for the second 4k bank.... since the 6507 sees these as the same address.

 

For more info on VCS memory layout, you might want to read thru the discussion here: http://atariage.com/forums/topic/27190-session-5-memory-architecture/

 

On boot up, the 650x series looks at $FFFC and $FFFD locations for the RESET vector. More info here: https://en.wikipedia.org/wiki/Interrupts_in_65xx_processors

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Posted (edited)

Thanks for the update.

Yah, I would suggest a jumper, physical switch etc for hard selecting between 2600 mode and enhanced mode.
I have to assume there's way to much legacy code that relies on those upper address lines being ignored, in their execution.

Edited by rbairos

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Posted (edited)

Okay so I have been working on this a little bit, how possible would it be to use the Tia out of spec, like by having it draw more than 262 lines, of course this natively would not display, but couldn't you use an fpga to take this and make it into a displayable picture,  or what about using two tia's together and have 525 lines? At this point the project has become more of a vcs based (video)computer than a console,  it currently has ~128k of ram usable, 32k to 6502, 32k ported through the ay38910 gpio, and the atmega 644 has 64k plus a few k's of eeprom, at this point I'm really interested in seeing what this could do, I already know it'll sound better with 5 voice sound, I'm sure with the right hardware one could get the tia to display something close nes graphics or something close the the 8bit line, especially looking at the demoscene, it's performance is limited by the vcs design limitations itself..

Edited by universal2600

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You're limited by the TV + NTSC combo.

 

The TIA will draw as many lines as you want it to.  No really.  The vertical resolution is purely software driven.  You could have *ANY* number of scan lines in each frame.  500?  1000?  1,000,000?  Sure.  No problem to do this on a stock VCS.  But the frame rate will be 15.7kHz / scan lines per frame.  E.g. at 1080 lines the frame rate would be about 14.5.  But the NTSC TVs can only display 262.5 lines per field and 525 lines per frame (= 2 fields) by spec.  Most TVs will go a little higher but not much...there are limits.  The fields happen at ~60Hz, the frames happen at ~30 Hz. Most 2600 programs only draw a single field of 262.0 lines at 60 Hz.  Many draw 2 (or more!) different fields of 262.0 lines...overlapped, not interlaced.  Using this multi-field technique you can have more sprites displayed but with added flicker.  2 fields = 30Hz flicker, 3 fields = 20Hz, 4 fields = 15Hz, etc.

 

You *can* get interlacing to work.  It's not hard to kludge it but some TVs won't like it.  It's not terribly hard to do it "right" but it takes up the whole processor during VSYNC (= 3 lines per field).  My interlace is rock solid on every TV and video test instrument I've tested with.  If you do a proper interlaced display you can get the full NTSC 525 lines @ 30 Hz (interlaced) out of a stock VCS.

 

At this point....do you want to just get more out of your heavily modified VCS (not really a VCS anymore), or do you want to build the best performing machine you can possibly build?  You can use more than one TIA, but you're still going to be drawing NTSC-esque images with that.  To get more lines, vertical or horizontal you're going to have to move away from NTSC TVs and the TIA.  Or do some clever signal smashing with the multiple TIAs.

 

Regarding the architecture limitations.....the VCS is really defined by the TIA.  That's your bottleneck.  The TIA will never be able to display NES quality graphics.  The architectural intent was too different.  You might want to look at the Maria if you want to have 3rd generation capability.  But since this really isn't a VCS anymore, why don't you just design a GPU to do what you want?  You already mentioned using an FPGA.  Doing a clean GPU design at the 8-bit computer generation level wouldn't be that hard.  Reproing existing graphics hardware (100% compatible) is probably harder.  And getting enough vintage stock graphics hardware glued together to do what you want might only be worth it for the challenge itself.

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Posted (edited)

I'm building mainly out of curiosity, really I have the 6502, 6532, tia, ay38910, 64k sram, and atmega 644, the 644 I would clock at 21.47727 (6x) tia clock and pretty much use it kinda like the Antic chip,  there's enough ram to store a full framebuffer, and allows me to use the 6502 to do other things, and i didn't mean that I could get the tia to produce nes like graphics, but produce something that (hopefully) looks and sounds way better than the vcs

 

 

 

 

 

 

 

PS I did at one point think about using the gtia and pokey to be honest.... And it's cheaper using this chipset, and all parts except the tia can be bought new 

Edited by universal2600

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