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Per the SN76489 data sheet, it needs 4 cycles to load a data value. I note from the schematic that its ready line is connected to the Z80's WAIT input.

 

I notice that the Z80 OUT will have been asserting the write input for 1.5 cycles before it tests WAIT. So it looks to me like it should end up inserting three WAIT cycles, making the entire machine cycle seven cycles long. Or, in net, adding three cycles to any OUT that is decoded to access the SN76489.

 

Is that a correct reading?

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